diff --git a/tridoracpu/tridoracpu.srcs/mem.v b/tridoracpu/tridoracpu.srcs/mem.v
index 2928a7d..2fe1b5f 100644
--- a/tridoracpu/tridoracpu.srcs/mem.v
+++ b/tridoracpu/tridoracpu.srcs/mem.v
@@ -91,8 +91,10 @@ module mem #(parameter ADDR_WIDTH = 32,
   // RAM1 $1000 - $FFFF 60K
   // RAM2 $10000 - $FFFFFFFF ~4GB
 
+  localparam RAM1_ADDR_WIDTH = 16;
+
   wire ram_cs = addr[ADDR_WIDTH-1:12] != { {(ADDR_WIDTH-12){1'b0}}};
-  wire ram1_cs = ram_cs && (addr[ADDR_WIDTH-1:16] == { {(ADDR_WIDTH-16){1'b0}}});
+  wire ram1_cs = ram_cs && (addr[ADDR_WIDTH-1:RAM1_ADDR_WIDTH] == { {(ADDR_WIDTH-RAM1_ADDR_WIDTH){1'b0}}});
   wire ram2_cs = ram_cs && !ram1_cs;
   wire rom_cs = !ram_cs && addr[11] == 1'b0;
   wire io_cs = !ram_cs && addr[11]  == 1'b1;
@@ -116,10 +118,10 @@ module mem #(parameter ADDR_WIDTH = 32,
   // test
   reg [1:0] wait_state;
 
-  ram32 #(.ADDR_WIDTH(16)) ram0  // 64KB RAM
+  ram32 #(.ADDR_WIDTH(RAM1_ADDR_WIDTH)) ram0  // 64KB RAM
   (
     .clk(clk),
-    .addr(addr[15:0]),
+    .addr(addr[RAM1_ADDR_WIDTH-1:0]),
     .data_out(ram_out),
     .read_enable(ram_read),
     .data_in(data_in),
diff --git a/tridoracpu/tridoracpu.xpr b/tridoracpu/tridoracpu.xpr
index 304490b..b0ba2bb 100644
--- a/tridoracpu/tridoracpu.xpr
+++ b/tridoracpu/tridoracpu.xpr
@@ -351,7 +351,9 @@
   <Runs Version="1" Minor="22">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -371,7 +373,9 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Best predicted directive for place_design." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Performance_Auto_1" Flow="Vivado Implementation 2024"/>
+        <StratHandle Name="Performance_Auto_1" Flow="Vivado Implementation 2024">
+          <Desc>Best predicted directive for place_design.</Desc>
+        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design">
           <Option Id="Directive">0</Option>