slederer/Tridora-CPU
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tridoracpu: trim down pins in constraints file

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- remove unnecessary I/O pins
- adjust top connections
This commit is contained in:
slederer 2025-02-28 02:32:37 +01:00
parent 2edd5679a1
commit b2f581c862
3 changed files with 52 additions and 247 deletions
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17
tridoracpu/tridoracpu.srcs/top_ccgm.v
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@ -6,11 +6,11 @@
//`define clkfreq 100000000
//`define clock clk_1hz
`define ENABLE_VGAFB
`define ENABLE_MICROSD
//`define ENABLE_MICROSD
module top(
input wire clk,
input wire rst,
input wire rst_n,
output wire led0,
input wire uart_txd_in,
output wire uart_rxd_out
@ -34,7 +34,6 @@ module top(
input wire sd_cd
`endif
);
reg [31:0] counter;
localparam ADDR_WIDTH = 32, WIDTH = 32,
@ -64,10 +63,10 @@ module top(
wire cpuclk, cpuclk_locked;
wire dram_refclk200;
wire pixclk = cpuclk;
cpu_clkgen cpuclk_0(~rst, clk, cpuclk, cpuclk_locked);
cpu_clkgen cpuclk_0(~rst_n, clk, cpuclk, cpuclk_locked);
mem #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(WIDTH)) mem0(
.clk(`clock), .rst_n(rst), .addr(mem_addr),
.clk(`clock), .rst_n(rst_n), .addr(mem_addr),
.data_out(mem_read_data), .read_enable(mem_read_enable),
.data_in(mem_write_data), .write_enable(mem_write_enable),
.io_enable(io_enable),
@ -89,7 +88,7 @@ module top(
assign fb_wr_en = fb_cs_en && mem_write_enable;
assign fb_wr_data = mem_write_data;
vgafb vgafb0(`clock, pixclk, rst,
vgafb vgafb0(`clock, pixclk, rst_n,
mem_addr[3:0], fb_rd_data, fb_wr_data,
fb_rd_en, fb_wr_en,
VGA_HS_O, VGA_VS_O, VGA_R, VGA_G, VGA_B);
@ -143,7 +142,7 @@ module top(
assign spi_tx_write = spi_cs && mem_write_enable && mem_write_data[8];
assign spi_tx_data = mem_write_data[7:0];
sdspi sdspi0(.clk(`clock), .reset(~rst),
sdspi sdspi0(.clk(`clock), .reset(~rst_n),
.tx_data(spi_tx_data), .rx_data(spi_rx_data),
.tx_ready(spi_tx_ready), .tx_empty(spi_tx_empty),
.rx_avail(spi_rx_avail), .rx_ovr(spi_rx_ovr),
@ -197,7 +196,7 @@ module top(
-1;
buart #(.CLKFREQ(`clkfreq)) uart0(`clock, rst,
buart #(.CLKFREQ(`clkfreq)) uart0(`clock, rst_n,
uart_baud,
uart_txd_in, uart_rxd_out,
uart_rx_clear, uart_tx_en,
@ -205,7 +204,7 @@ module top(
uart_tx_data, uart_rx_data);
// CPU -----------------------------------------------------------------
stackcpu cpu0(.clk(`clock), .rst(rst), .irq(irq),
stackcpu cpu0(.clk(`clock), .rst(rst_n), .irq(irq),
.addr(mem_addr),
.data_in(mem_read_data), .read_enable(mem_read_enable),
.data_out(mem_write_data), .write_enable(mem_write_enable),