import Vivado project, rearrange Verilog sources
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29 changed files with 789 additions and 742 deletions
262
tridoracpu/tridoracpu.srcs/uart.v
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262
tridoracpu/tridoracpu.srcs/uart.v
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/*
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Copyright (c) 2010-2020, James Bowman
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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* Neither the name of swapforth nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`default_nettype none
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//`define def_clkfreq 100000000
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`define def_clkfreq 83333333
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module baudgen(
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input wire clk,
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input wire resetq,
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input wire [31:0] baud,
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input wire restart,
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output wire ser_clk);
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parameter CLKFREQ = `def_clkfreq;
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wire [38:0] aclkfreq = CLKFREQ;
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reg [38:0] d;
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wire [38:0] dInc = d[38] ? ({4'd0, baud}) : (({4'd0, baud}) - aclkfreq);
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wire [38:0] dN = restart ? 0 : (d + dInc);
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wire fastclk = ~d[38];
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assign ser_clk = fastclk;
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always @(negedge resetq or posedge clk)
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begin
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if (!resetq) begin
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d <= 0;
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end else begin
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d <= dN;
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end
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end
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endmodule
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/*
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-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+----
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| | | | | | | | | | | |
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|start| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |stop1|stop2|
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| | | | | | | | | | | ? |
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+-----+-----+-----+-----+-----+-----+-----+-----+-----+ +
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*/
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module uart(
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input wire clk, // System clock
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input wire resetq,
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// Outputs
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output wire uart_busy, // High means UART is transmitting
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output reg uart_tx, // UART transmit wire
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// Inputs
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input wire [31:0] baud,
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input wire uart_wr_i, // Raise to transmit byte
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input wire [7:0] uart_dat_i // 8-bit data
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);
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parameter CLKFREQ = `def_clkfreq;
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reg [3:0] bitcount;
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reg [8:0] shifter;
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assign uart_busy = |bitcount;
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wire sending = |bitcount;
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wire ser_clk;
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wire starting = uart_wr_i & ~uart_busy;
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baudgen #(.CLKFREQ(CLKFREQ)) _baudgen(
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.clk(clk),
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.resetq(resetq),
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.baud(baud),
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.restart(1'b0),
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.ser_clk(ser_clk));
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always @(negedge resetq or posedge clk)
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begin
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if (!resetq) begin
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uart_tx <= 1;
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bitcount <= 0;
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shifter <= 0;
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end else begin
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if (starting) begin
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shifter <= { uart_dat_i[7:0], 1'b0 };
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bitcount <= 1 + 8 + 1;
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end
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if (sending & ser_clk) begin
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{ shifter, uart_tx } <= { 1'b1, shifter };
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bitcount <= bitcount - 4'd1;
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end
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end
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end
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endmodule
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module rxuart(
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input wire clk,
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input wire resetq,
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input wire [31:0] baud,
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input wire uart_rx, // UART recv wire
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input wire rd, // read strobe
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output wire valid, // has data
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output wire [7:0] data); // data
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parameter CLKFREQ = `def_clkfreq;
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reg [4:0] bitcount;
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reg [7:0] shifter;
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// On starting edge, wait 3 half-bits then sample, and sample every 2 bits thereafter
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wire idle = &bitcount;
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wire sample;
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reg [2:0] hh = 3'b111;
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wire [2:0] hhN = {hh[1:0], uart_rx};
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wire startbit = idle & (hhN[2:1] == 2'b10);
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wire [7:0] shifterN = sample ? {hh[1], shifter[7:1]} : shifter;
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wire ser_clk;
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baudgen #(.CLKFREQ(CLKFREQ)) _baudgen(
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.clk(clk),
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.baud({baud[30:0], 1'b0}),
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.resetq(resetq),
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.restart(startbit),
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.ser_clk(ser_clk));
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assign valid = (bitcount == 18);
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reg [4:0] bitcountN;
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always @*
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if (startbit)
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bitcountN = 0;
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else if (!idle & !valid & ser_clk)
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bitcountN = bitcount + 5'd1;
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else if (valid & rd)
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bitcountN = 5'b11111;
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else
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bitcountN = bitcount;
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// 3,5,7,9,11,13,15,17
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assign sample = (bitcount > 2) & bitcount[0] & !valid & ser_clk;
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assign data = shifter;
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always @(negedge resetq or posedge clk)
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begin
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if (!resetq) begin
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hh <= 3'b111;
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bitcount <= 5'b11111;
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shifter <= 0;
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end else begin
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hh <= hhN;
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bitcount <= bitcountN;
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shifter <= shifterN;
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end
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end
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endmodule
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module fifo_rxuart(
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input wire clk,
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input wire resetq,
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input wire [31:0] baud,
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input wire uart_rx, // UART recv wire
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input wire rd, // read strobe
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output wire valid, // has data
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output wire [7:0] data); // data
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parameter CLKFREQ = `def_clkfreq;
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localparam ADDR_WIDTH = 6;
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localparam DATA_WIDTH = 8;
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reg fifo_wr_en;
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(*KEEP*) wire fifo_rd_en, fifo_full, fifo_empty;
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wire [DATA_WIDTH-1:0] fifo_wr_data, fifo_rd_data;
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(*KEEP*) wire rx_avail;
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assign valid = !fifo_empty;
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assign data = fifo_rd_data;
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assign fifo_rd_en = rd;
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fifo #(.ADDR_WIDTH(ADDR_WIDTH)) rx_fifo(clk, ~resetq,
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fifo_wr_en, fifo_rd_en,
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fifo_wr_data, fifo_rd_data,
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fifo_full,
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fifo_empty
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);
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rxuart #(.CLKFREQ(CLKFREQ)) _rx (
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.clk(clk),
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.resetq(resetq),
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.baud(baud),
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.uart_rx(uart_rx),
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.rd(fifo_wr_en), // strobe read signal on fifo write
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.valid(rx_avail),
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.data(fifo_wr_data));
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always @(posedge clk)
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begin
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if (!resetq)
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fifo_wr_en <= 0;
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else if(!fifo_wr_en && rx_avail) // ILA shows fifo_wr_en stays 0 ??
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fifo_wr_en <= 1; // pulse fifo_wr_en for one clock
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else // rx_avail goes zero one clock later
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fifo_wr_en <= 0;
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end
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endmodule
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module buart(
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input wire clk,
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input wire resetq,
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input wire [31:0] baud,
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input wire rx, // recv wire
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output wire tx, // xmit wire
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input wire rd, // read strobe
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input wire wr, // write strobe
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output wire valid, // has recv data
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output wire busy, // is transmitting
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input wire [7:0] tx_data,
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output wire [7:0] rx_data // data
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);
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parameter CLKFREQ = `def_clkfreq;
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fifo_rxuart #(.CLKFREQ(CLKFREQ)) _rx (
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.clk(clk),
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.resetq(resetq),
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.baud(baud),
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.uart_rx(rx),
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.rd(rd),
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.valid(valid),
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.data(rx_data));
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uart #(.CLKFREQ(CLKFREQ)) _tx (
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.clk(clk),
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.resetq(resetq),
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.baud(baud),
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.uart_busy(busy),
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.uart_tx(tx),
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.uart_wr_i(wr),
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.uart_dat_i(tx_data));
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endmodule
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