From a441e7e0421a6fd6f3d305d33f332d1b13b8f473 Mon Sep 17 00:00:00 2001 From: slederer Date: Fri, 27 Sep 2024 22:13:23 +0200 Subject: [PATCH] import Vivado project, rearrange Verilog sources --- .gitignore | 27 +- rtl/arty-a7/Arty_C_mig.ucf | 48 -- rtl/arty-a7/tridoracpu.tcl | 683 ------------------ .../sdspi_testbench_behav.wcfg | 0 tridoracpu/testbench_behav.wcfg | 272 +++++++ .../testbench_behav1.wcfg | 0 .../tridoracpu.srcs}/Arty-A7-35-Master.xdc | 0 .../tridoracpu.srcs}/bram_tdp.v | 0 .../tridoracpu.srcs}/cpuclk.v | 0 .../tridoracpu.srcs}/display_clock.v | 0 .../tridoracpu.srcs}/dram_bridge.v | 0 .../src => tridoracpu/tridoracpu.srcs}/fifo.v | 0 .../tridoracpu.srcs}/fifo_testbench.v | 0 .../tridoracpu.srcs}/irqctrl.v | 0 {rtl/src => tridoracpu/tridoracpu.srcs}/mem.v | 0 .../tridoracpu.srcs}/mig_dram_0/mig_a.prj | 0 .../tridoracpu.srcs}/mig_dram_0/mig_b.prj | 0 .../tridoracpu.srcs}/palette.v | 0 .../tridoracpu.srcs}/sdspi.v | 0 .../tridoracpu.srcs}/sdspi_testbench.v | 0 tridoracpu/tridoracpu.srcs/sfifo.v | 84 +++ .../tridoracpu.srcs}/stack.v | 0 .../tridoracpu.srcs}/stackcpu.v | 0 .../tridoracpu.srcs}/testbench.v | 0 {rtl/src => tridoracpu/tridoracpu.srcs}/top.v | 0 .../src => tridoracpu/tridoracpu.srcs}/uart.v | 0 .../tridoracpu.srcs}/uart_tb.v | 0 .../tridoracpu.srcs}/vgafb.v | 0 tridoracpu/tridoracpu.xpr | 417 +++++++++++ 29 files changed, 789 insertions(+), 742 deletions(-) delete mode 100644 rtl/arty-a7/Arty_C_mig.ucf delete mode 100644 rtl/arty-a7/tridoracpu.tcl rename {rtl/arty-a7 => tridoracpu}/sdspi_testbench_behav.wcfg (100%) create mode 100644 tridoracpu/testbench_behav.wcfg rename {rtl/arty-a7 => tridoracpu}/testbench_behav1.wcfg (100%) rename {rtl/arty-a7 => tridoracpu/tridoracpu.srcs}/Arty-A7-35-Master.xdc (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/bram_tdp.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/cpuclk.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/display_clock.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/dram_bridge.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/fifo.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/fifo_testbench.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/irqctrl.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/mem.v (100%) rename {rtl/arty-a7 => tridoracpu/tridoracpu.srcs}/mig_dram_0/mig_a.prj (100%) rename {rtl/arty-a7 => tridoracpu/tridoracpu.srcs}/mig_dram_0/mig_b.prj (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/palette.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/sdspi.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/sdspi_testbench.v (100%) create mode 100644 tridoracpu/tridoracpu.srcs/sfifo.v rename {rtl/src => tridoracpu/tridoracpu.srcs}/stack.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/stackcpu.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/testbench.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/top.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/uart.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/uart_tb.v (100%) rename {rtl/src => tridoracpu/tridoracpu.srcs}/vgafb.v (100%) create mode 100644 tridoracpu/tridoracpu.xpr diff --git a/.gitignore b/.gitignore index e13b46b..2096fdb 100644 --- a/.gitignore +++ b/.gitignore @@ -2,6 +2,7 @@ pcomp/*.s progs/*.s tests/*.s examples/*.s +!runtime.s *.o *.exe *.bin @@ -21,14 +22,18 @@ sine.pas graph1.pas graph2.pas chase.pas -!runtime.s -**/tridoracpu.*/ -rtl/arty-a7/mig_dram_0/_tmp/* -rtl/arty-a7/mig_dram_0/doc/* -rtl/arty-a7/mig_dram_0/mig_dram_0* -rtl/arty-a7/mig_dram_0/xil_txt.* -rtl/arty-a7/mig_dram_0/*.veo -rtl/arty-a7/mig_dram_0/*.tcl -rtl/arty-a7/mig_dram_0/*.xml -rtl/arty-a7/mig_dram_0/*.v -rtl/arty-a7/mig_dram_0/*.vhdl +**/tridoracpu.cache/ +**/tridoracpu.hw/ +**/tridoracpu.ip_user_files/ +**/tridoracpu.runs/ +*.log +*.jou +**/mig_dram_0/_tmp/* +**/mig_dram_0/doc/* +**/mig_dram_0/mig_dram_0* +**/mig_dram_0/xil_txt.* +**/mig_dram_0/*.veo +**/mig_dram_0/*.tcl +**/mig_dram_0/*.xml +**/mig_dram_0/*.v +**/mig_dram_0/*.vhdl diff --git a/rtl/arty-a7/Arty_C_mig.ucf b/rtl/arty-a7/Arty_C_mig.ucf deleted file mode 100644 index 5a36c18..0000000 --- a/rtl/arty-a7/Arty_C_mig.ucf +++ /dev/null @@ -1,48 +0,0 @@ -NET "ddr3_dq[0]" LOC = "K5" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[1]" LOC = "L3" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[2]" LOC = "K3" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[3]" LOC = "L6" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[4]" LOC = "M3" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[5]" LOC = "M1" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[6]" LOC = "L4" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[7]" LOC = "M2" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[8]" LOC = "V4" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[9]" LOC = "T5" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[10]" LOC = "U4" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[11]" LOC = "V5" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[12]" LOC = "V1" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[13]" LOC = "T3" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[14]" LOC = "U3" | IOSTANDARD = SSTL135 ; -NET "ddr3_dq[15]" LOC = "R3" | IOSTANDARD = SSTL135 ; -NET "ddr3_dm[0]" LOC = "L1" | IOSTANDARD = SSTL135 ; -NET "ddr3_dm[1]" LOC = "U1" | IOSTANDARD = SSTL135 ; -NET "ddr3_dqs_p[0]" LOC = "N2" | IOSTANDARD = DIFF_SSTL135 ; -NET "ddr3_dqs_n[0]" LOC = "N1" | IOSTANDARD = DIFF_SSTL135 ; -NET "ddr3_dqs_p[1]" LOC = "U2" | IOSTANDARD = DIFF_SSTL135 ; -NET "ddr3_dqs_n[1]" LOC = "V2" | IOSTANDARD = DIFF_SSTL135 ; -NET "ddr3_addr[13]" LOC = "T8" | IOSTANDARD = SSTL135 ; -NET "ddr3_addr[12]" LOC = "T6" | IOSTANDARD = SSTL135 ; -NET "ddr3_addr[11]" LOC = "U6" | IOSTANDARD = SSTL135 ; -NET "ddr3_addr[10]" LOC = "R6" | IOSTANDARD = SSTL135 ; -NET "ddr3_addr[9]" LOC = "V7" | IOSTANDARD = SSTL135 ; -NET "ddr3_addr[8]" LOC = "R8" | IOSTANDARD = SSTL135 ; -NET "ddr3_addr[7]" LOC = "U7" | IOSTANDARD = SSTL135 ; -NET "ddr3_addr[6]" LOC = "V6" | IOSTANDARD = SSTL135 ; -NET "ddr3_addr[5]" LOC = "R7" | IOSTANDARD = SSTL135 ; -NET "ddr3_addr[4]" LOC = "N6" | IOSTANDARD = SSTL135 ; -NET "ddr3_addr[3]" LOC = "T1" | IOSTANDARD = SSTL135 ; -NET "ddr3_addr[2]" LOC = "N4" | IOSTANDARD = SSTL135 ; -NET "ddr3_addr[1]" LOC = "M6" | IOSTANDARD = SSTL135 ; -NET "ddr3_addr[0]" LOC = "R2" | IOSTANDARD = SSTL135 ; -NET "ddr3_ba[2]" LOC = "P2" | IOSTANDARD = SSTL135 ; -NET "ddr3_ba[1]" LOC = "P4" | IOSTANDARD = SSTL135 ; -NET "ddr3_ba[0]" LOC = "R1" | IOSTANDARD = SSTL135 ; -NET "ddr3_ck_p[0]" LOC = "U9" | IOSTANDARD = DIFF_SSTL135 ; -NET "ddr3_ck_n[0]" LOC = "V9" | IOSTANDARD = DIFF_SSTL135 ; -NET "ddr3_ras_n" LOC = "P3" | IOSTANDARD = SSTL135 ; -NET "ddr3_cas_n" LOC = "M4" | IOSTANDARD = SSTL135 ; -NET "ddr3_we_n" LOC = "P5" | IOSTANDARD = SSTL135 ; -NET "ddr3_reset_n" LOC = "K6" | IOSTANDARD = SSTL135 ; -NET "ddr3_cke[0]" LOC = "N5" | IOSTANDARD = SSTL135 ; -NET "ddr3_odt[0]" LOC = "R5" | IOSTANDARD = SSTL135 ; -NET "ddr3_cs_n[0]" LOC = "U8" | IOSTANDARD = SSTL135 ; diff --git a/rtl/arty-a7/tridoracpu.tcl b/rtl/arty-a7/tridoracpu.tcl deleted file mode 100644 index 46ab1d1..0000000 --- a/rtl/arty-a7/tridoracpu.tcl +++ /dev/null @@ -1,683 +0,0 @@ -#***************************************************************************************** -# Vivado (TM) v2020.1 (64-bit) -# -# tridoracpu.tcl: Tcl script for re-creating project 'tridoracpu' -# -# Generated by Vivado on Sat Sep 14 23:58:12 +0200 2024 -# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 -# -# This file contains the Vivado Tcl commands for re-creating the project to the state* -# when this script was generated. In order to re-create the project, please source this -# file in the Vivado Tcl Shell. -# -# * Note that the runs in the created project will be configured the same way as the -# original project, however they will not be launched automatically. To regenerate the -# run results please launch the synthesis/implementation runs as needed. -# -#***************************************************************************************** - -# uncomment next two statements if you have never initialized the Xilinx Board Store -# this will take quite some time -#xhub::refresh_catalog [xhub::get_xstores xilinx_board_store] -#xhub::install [xhub::get_xitems] - -# Set the reference directory for source file relative paths -set origin_dir "change_this_to_your_rtl_directory" - -set xilinx_board_store_dir [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]] -set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]] - -# Use origin directory path location variable, if specified in the tcl shell -if { [info exists ::origin_dir_loc] } { - set origin_dir $::origin_dir_loc -} - -# Set the project name -set _xil_proj_name_ "tridoracpu" - -# Use project name variable, if specified in the tcl shell -if { [info exists ::user_project_name] } { - set _xil_proj_name_ $::user_project_name -} - -variable script_file -set script_file "tridoracpu.tcl" - -# Help information for this script -proc print_help {} { - variable script_file - puts "\nDescription:" - puts "Recreate a Vivado project from this script. The created project will be" - puts "functionally equivalent to the original project for which this script was" - puts "generated. The script contains commands for creating a project, filesets," - puts "runs, adding/importing sources and setting properties on various objects.\n" - puts "Syntax:" - puts "$script_file" - puts "$script_file -tclargs \[--origin_dir \]" - puts "$script_file -tclargs \[--project_name \]" - puts "$script_file -tclargs \[--help\]\n" - puts "Usage:" - puts "Name Description" - puts "-------------------------------------------------------------------------" - puts "\[--origin_dir \] Determine source file paths wrt this path. Default" - puts " origin_dir path value is \".\", otherwise, the value" - puts " that was set with the \"-paths_relative_to\" switch" - puts " when this script was generated.\n" - puts "\[--project_name \] Create project with the specified name. Default" - puts " name is the name of the project from where this" - puts " script was generated.\n" - puts "\[--help\] Print help information for this script" - puts "-------------------------------------------------------------------------\n" - exit 0 -} - -if { $::argc > 0 } { - for {set i 0} {$i < $::argc} {incr i} { - set option [string trim [lindex $::argv $i]] - switch -regexp -- $option { - "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } - "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } - "--help" { print_help } - default { - if { [regexp {^-} $option] } { - puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" - return 1 - } - } - } - } -} - -# Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "${origin_dir}/arty-a7"]" - -# Create project -create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a35ticsg324-1L - -# Set the directory path for the new project -set proj_dir [get_property directory [current_project]] - -# Set project properties -set obj [current_project] -#set_property -name "board_part_repo_paths" -value "[file normalize "$xilinx_board_store_dir"]" -objects $obj -set_property -name "board_part" -value "digilentinc.com:arty-a7-35:part0:1.0" -objects $obj -set_property -name "default_lib" -value "xil_defaultlib" -objects $obj -set_property -name "enable_vhdl_2008" -value "1" -objects $obj -set_property -name "ip_cache_permissions" -value "read write" -objects $obj -set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj -set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj -set_property -name "platform.board_id" -value "arty-a7-35" -objects $obj -set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj -set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj -set_property -name "simulator_language" -value "Mixed" -objects $obj -set_property -name "source_mgmt_mode" -value "DisplayOnly" -objects $obj -set_property -name "webtalk.activehdl_export_sim" -value "4" -objects $obj -set_property -name "webtalk.ies_export_sim" -value "4" -objects $obj -set_property -name "webtalk.modelsim_export_sim" -value "4" -objects $obj -set_property -name "webtalk.questa_export_sim" -value "4" -objects $obj -set_property -name "webtalk.riviera_export_sim" -value "4" -objects $obj -set_property -name "webtalk.vcs_export_sim" -value "4" -objects $obj -set_property -name "webtalk.xsim_export_sim" -value "4" -objects $obj -set_property -name "webtalk.xsim_launch_sim" -value "537" -objects $obj - -# Create 'sources_1' fileset (if not found) -if {[string equal [get_filesets -quiet sources_1] ""]} { - create_fileset -srcset sources_1 -} - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - [file normalize "${origin_dir}/src/uart.v"] \ -] -add_files -norecurse -fileset $obj $files - -# Add local files from the original project (-no_copy_sources specified) -set files [list \ - [file normalize "${origin_dir}/src/cpuclk.v" ]\ - [file normalize "${origin_dir}/src/display_clock.v" ]\ - [file normalize "${origin_dir}/src/mem.v" ]\ - [file normalize "${origin_dir}/src/stack.v" ]\ - [file normalize "${origin_dir}/src/stackcpu.v" ]\ - [file normalize "${origin_dir}/src/vgafb.v" ]\ - [file normalize "${origin_dir}/src/top.v" ]\ - [file normalize "${origin_dir}/src/testbench.v" ]\ - [file normalize "${orig_proj_dir}/rom.mem" ]\ - [file normalize "${orig_proj_dir}/mig_dram_0/mig_a.prj" ]\ - [file normalize "${orig_proj_dir}/mig_dram_0/mig_b.prj" ]\ - [file normalize "${origin_dir}/src/dram_bridge.v" ]\ - [file normalize "${origin_dir}/src/sdspi.v" ]\ - [file normalize "${origin_dir}/src/bram_tdp.v" ]\ - [file normalize "${origin_dir}/src/palette.v" ]\ - [file normalize "${origin_dir}/src/irqctrl.v" ]\ - [file normalize "${origin_dir}/src/fifo.v" ]\ - [file normalize "${origin_dir}/src/fifo_testbench.v" ]\ - [file normalize "${origin_dir}/src/sdspi_testbench.v" ]\ -] -set added_files [add_files -fileset sources_1 $files] - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/src/uart.v" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "used_in" -value "synthesis implementation" -objects $file_obj -set_property -name "used_in_simulation" -value "0" -objects $file_obj - - -# Set 'sources_1' fileset file properties for local files -set file "src/cpuclk.v" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "used_in" -value "synthesis implementation" -objects $file_obj -set_property -name "used_in_simulation" -value "0" -objects $file_obj - -set file "src/display_clock.v" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "is_enabled" -value "0" -objects $file_obj - -set file "src/mem.v" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "used_in" -value "synthesis implementation" -objects $file_obj -set_property -name "used_in_simulation" -value "0" -objects $file_obj - -set file "src/stack.v" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "used_in" -value "synthesis implementation" -objects $file_obj -set_property -name "used_in_simulation" -value "0" -objects $file_obj - -set file "src/stackcpu.v" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "used_in" -value "synthesis implementation" -objects $file_obj -set_property -name "used_in_simulation" -value "0" -objects $file_obj - -set file "src/vgafb.v" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "used_in" -value "synthesis implementation" -objects $file_obj -set_property -name "used_in_simulation" -value "0" -objects $file_obj - -set file "src/top.v" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "used_in" -value "synthesis implementation" -objects $file_obj -set_property -name "used_in_simulation" -value "0" -objects $file_obj - -set file "src/testbench.v" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "used_in" -value "" -objects $file_obj -set_property -name "used_in_implementation" -value "0" -objects $file_obj -set_property -name "used_in_simulation" -value "0" -objects $file_obj -set_property -name "used_in_synthesis" -value "0" -objects $file_obj - -set file "arty-a7/rom.mem" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "file_type" -value "Memory File" -objects $file_obj - -set file "arty-a7/mig_dram_0/mig_a.prj" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "scoped_to_cells" -value "mig_dram_0" -objects $file_obj - -set file "arty-a7/mig_dram_0/mig_b.prj" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "scoped_to_cells" -value "mig_dram_0" -objects $file_obj - -set file "src/dram_bridge.v" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "used_in" -value "synthesis implementation" -objects $file_obj -set_property -name "used_in_simulation" -value "0" -objects $file_obj - -set file "src/palette.v" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "used_in" -value "synthesis implementation" -objects $file_obj -set_property -name "used_in_simulation" -value "0" -objects $file_obj - -set file "src/irqctrl.v" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "used_in" -value "synthesis implementation" -objects $file_obj -set_property -name "used_in_simulation" -value "0" -objects $file_obj - -set file "src/fifo_testbench.v" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "used_in" -value "" -objects $file_obj -set_property -name "used_in_implementation" -value "0" -objects $file_obj -set_property -name "used_in_simulation" -value "0" -objects $file_obj -set_property -name "used_in_synthesis" -value "0" -objects $file_obj - - -# Set 'sources_1' fileset properties -set obj [get_filesets sources_1] -set_property -name "top" -value "top" -objects $obj -set_property -name "top_auto_set" -value "0" -objects $obj - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -# Add local files from the original project (-no_copy_sources specified) -set files [list \ - [file normalize "${orig_proj_dir}/mig_dram_0/mig_dram_0.xci" ]\ -] -set added_files [add_files -fileset sources_1 $files] - -# Set 'sources_1' fileset file properties for remote files -# None - -# Set 'sources_1' fileset file properties for local files -set file "arty-a7/mig_dram_0/mig_dram_0.xci" -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} -set_property -name "used_in" -value "synthesis implementation" -objects $file_obj -set_property -name "used_in_simulation" -value "0" -objects $file_obj - - -# Create 'constrs_1' fileset (if not found) -if {[string equal [get_filesets -quiet constrs_1] ""]} { - create_fileset -constrset constrs_1 -} - -# Set 'constrs_1' fileset object -set obj [get_filesets constrs_1] - -# Add/Import constrs file and set constrs file properties -set file "[file normalize ${origin_dir}/arty-a7/Arty-A7-35-Master.xdc]" -set file_added [add_files -norecurse -fileset $obj [list $file]] -set file "$origin_dir/arty-a7/Arty-A7-35-Master.xdc" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] -set_property -name "file_type" -value "XDC" -objects $file_obj - -# Set 'constrs_1' fileset properties -set obj [get_filesets constrs_1] -set_property -name "target_constrs_file" -value "$orig_proj_dir/Arty-A7-35-Master.xdc" -objects $obj -set_property -name "target_ucf" -value "$orig_proj_dir/Arty-A7-35-Master.xdc" -objects $obj - -# Create 'sim_1' fileset (if not found) -if {[string equal [get_filesets -quiet sim_1] ""]} { - create_fileset -simset sim_1 -} - -# Set 'sim_1' fileset object -set obj [get_filesets sim_1] -# Add local files from the original project (-no_copy_sources specified) -set files [list \ - [file normalize "${origin_dir}/src/uart_tb.v" ]\ - [file normalize "${orig_proj_dir}/testbench_behav1.wcfg" ]\ -] -set added_files [add_files -fileset sim_1 $files] - -# Set 'sim_1' fileset file properties for remote files -# None - -# Set 'sim_1' fileset file properties for local files -set file [file normalize "${origin_dir}/src/uart_tb.v"] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property -name "used_in" -value "" -objects $file_obj -set_property -name "used_in_implementation" -value "0" -objects $file_obj -set_property -name "used_in_simulation" -value "0" -objects $file_obj -set_property -name "used_in_synthesis" -value "0" -objects $file_obj - - -# Set 'sim_1' fileset properties -set obj [get_filesets sim_1] -set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj -set_property -name "nl.mode" -value "funcsim" -objects $obj -set_property -name "top" -value "testbench" -objects $obj -set_property -name "top_lib" -value "xil_defaultlib" -objects $obj - -# Create 'sim_fifo' fileset (if not found) -if {[string equal [get_filesets -quiet sim_fifo] ""]} { - create_fileset -simset sim_fifo -} - -# Set 'sim_fifo' fileset object -set obj [get_filesets sim_fifo] -# Add local files from the original project (-no_copy_sources specified) -set files [list \ - [file normalize "${origin_dir}/src/fifo.v" ]\ - [file normalize "${origin_dir}/src/fifo_testbench.v" ]\ -] -set added_files [add_files -fileset sim_fifo $files] - -# Set 'sim_fifo' fileset file properties for remote files -# None - -# Set 'sim_fifo' fileset file properties for local files -# None - -# Set 'sim_fifo' fileset properties -set obj [get_filesets sim_fifo] -set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj -set_property -name "top" -value "fifo_testbench" -objects $obj -set_property -name "top_auto_set" -value "0" -objects $obj - -# Create 'sim_sdspi' fileset (if not found) -if {[string equal [get_filesets -quiet sim_sdspi] ""]} { - create_fileset -simset sim_sdspi -} - -# Set 'sim_sdspi' fileset object -set obj [get_filesets sim_sdspi] -# Add local files from the original project (-no_copy_sources specified) -set files [list \ - [file normalize "${orig_proj_dir}/sdspi_testbench_behav.wcfg" ]\ -] -set added_files [add_files -fileset sim_sdspi $files] - -# Set 'sim_sdspi' fileset file properties for remote files -# None - -# Set 'sim_sdspi' fileset file properties for local files -# None - -# Set 'sim_sdspi' fileset properties -set obj [get_filesets sim_sdspi] -set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj -set_property -name "sim_mode" -value "post-synthesis" -objects $obj -set_property -name "top" -value "sdspi_testbench" -objects $obj -set_property -name "top_auto_set" -value "0" -objects $obj -set_property -name "top_lib" -value "xil_defaultlib" -objects $obj -set_property -name "xsim.simulate.runtime" -value "10ms" -objects $obj - -# Set 'utils_1' fileset object -set obj [get_filesets utils_1] -# Empty (no sources present) - -# Set 'utils_1' fileset properties -set obj [get_filesets utils_1] - -# Create 'synth_1' run (if not found) -if {[string equal [get_runs -quiet synth_1] ""]} { - create_run -name synth_1 -part xc7a35ticsg324-1L -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 -} else { - set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] - set_property flow "Vivado Synthesis 2020" [get_runs synth_1] -} -set obj [get_runs synth_1] -set_property set_report_strategy_name 1 $obj -set_property report_strategy {Vivado Synthesis Default Reports} $obj -set_property set_report_strategy_name 0 $obj -# Create 'synth_1_synth_report_utilization_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { - create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 -} -set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] -if { $obj != "" } { - -} -set obj [get_runs synth_1] -set_property -name "needs_refresh" -value "1" -objects $obj -set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj - -# set the current synth run -current_run -synthesis [get_runs synth_1] - -# Create 'impl_1' run (if not found) -if {[string equal [get_runs -quiet impl_1] ""]} { - create_run -name impl_1 -part xc7a35ticsg324-1L -flow {Vivado Implementation 2020} -strategy "Performance_RefinePlacement" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 -} else { - set_property strategy "Performance_RefinePlacement" [get_runs impl_1] - set_property flow "Vivado Implementation 2020" [get_runs impl_1] -} -set obj [get_runs impl_1] -set_property set_report_strategy_name 1 $obj -set_property report_strategy {Vivado Implementation Default Reports} $obj -set_property set_report_strategy_name 0 $obj -# Create 'impl_1_init_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] -if { $obj != "" } { -set_property -name "is_enabled" -value "0" -objects $obj -set_property -name "options.max_paths" -value "10" -objects $obj - -} -# Create 'impl_1_opt_report_drc_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { - create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] -if { $obj != "" } { - -} -# Create 'impl_1_opt_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] -if { $obj != "" } { -set_property -name "is_enabled" -value "0" -objects $obj -set_property -name "options.max_paths" -value "10" -objects $obj - -} -# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] -if { $obj != "" } { -set_property -name "is_enabled" -value "0" -objects $obj -set_property -name "options.max_paths" -value "10" -objects $obj - -} -# Create 'impl_1_place_report_io_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { - create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] -if { $obj != "" } { - -} -# Create 'impl_1_place_report_utilization_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { - create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] -if { $obj != "" } { - -} -# Create 'impl_1_place_report_control_sets_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { - create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] -if { $obj != "" } { -set_property -name "options.verbose" -value "1" -objects $obj - -} -# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { - create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] -if { $obj != "" } { -set_property -name "is_enabled" -value "0" -objects $obj - -} -# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { - create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] -if { $obj != "" } { -set_property -name "is_enabled" -value "0" -objects $obj - -} -# Create 'impl_1_place_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] -if { $obj != "" } { -set_property -name "is_enabled" -value "0" -objects $obj -set_property -name "options.max_paths" -value "10" -objects $obj - -} -# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] -if { $obj != "" } { -set_property -name "is_enabled" -value "0" -objects $obj -set_property -name "options.max_paths" -value "10" -objects $obj - -} -# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] -if { $obj != "" } { -set_property -name "is_enabled" -value "0" -objects $obj -set_property -name "options.max_paths" -value "10" -objects $obj - -} -# Create 'impl_1_route_report_drc_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { - create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] -if { $obj != "" } { - -} -# Create 'impl_1_route_report_methodology_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { - create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] -if { $obj != "" } { - -} -# Create 'impl_1_route_report_power_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { - create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] -if { $obj != "" } { - -} -# Create 'impl_1_route_report_route_status_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { - create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] -if { $obj != "" } { - -} -# Create 'impl_1_route_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] -if { $obj != "" } { -set_property -name "options.max_paths" -value "10" -objects $obj - -} -# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { - create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] -if { $obj != "" } { - -} -# Create 'impl_1_route_report_clock_utilization_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { - create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] -if { $obj != "" } { - -} -# Create 'impl_1_route_report_bus_skew_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { - create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] -if { $obj != "" } { -set_property -name "options.warn_on_violation" -value "1" -objects $obj - -} -# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] -if { $obj != "" } { -set_property -name "options.max_paths" -value "10" -objects $obj -set_property -name "options.warn_on_violation" -value "1" -objects $obj - -} -# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { - create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 -} -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] -if { $obj != "" } { -set_property -name "options.warn_on_violation" -value "1" -objects $obj - -} -set obj [get_runs impl_1] -set_property -name "needs_refresh" -value "1" -objects $obj -set_property -name "strategy" -value "Performance_RefinePlacement" -objects $obj -set_property -name "steps.place_design.args.directive" -value "ExtraPostPlacementOpt" -objects $obj -set_property -name "steps.phys_opt_design.args.directive" -value "Explore" -objects $obj -set_property -name "steps.route_design.args.directive" -value "Explore" -objects $obj -set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj -set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj -set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj - -# set the current impl run -current_run -implementation [get_runs impl_1] - -puts "INFO: Project created:${_xil_proj_name_}" -# Create 'drc_1' gadget (if not found) -if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { -create_dashboard_gadget -name {drc_1} -type drc -} -set obj [get_dashboard_gadgets [ list "drc_1" ] ] -set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj - -# Create 'methodology_1' gadget (if not found) -if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { -create_dashboard_gadget -name {methodology_1} -type methodology -} -set obj [get_dashboard_gadgets [ list "methodology_1" ] ] -set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj - -# Create 'power_1' gadget (if not found) -if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { -create_dashboard_gadget -name {power_1} -type power -} -set obj [get_dashboard_gadgets [ list "power_1" ] ] -set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj - -# Create 'timing_1' gadget (if not found) -if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { -create_dashboard_gadget -name {timing_1} -type timing -} -set obj [get_dashboard_gadgets [ list "timing_1" ] ] -set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj - -# Create 'utilization_1' gadget (if not found) -if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { -create_dashboard_gadget -name {utilization_1} -type utilization -} -set obj [get_dashboard_gadgets [ list "utilization_1" ] ] -set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj -set_property -name "run.step" -value "synth_design" -objects $obj -set_property -name "run.type" -value "synthesis" -objects $obj - -# Create 'utilization_2' gadget (if not found) -if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { -create_dashboard_gadget -name {utilization_2} -type utilization -} -set obj [get_dashboard_gadgets [ list "utilization_2" ] ] -set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj - -move_dashboard_gadget -name {utilization_1} -row 0 -col 0 -move_dashboard_gadget -name {power_1} -row 1 -col 0 -move_dashboard_gadget -name {drc_1} -row 2 -col 0 -move_dashboard_gadget -name {timing_1} -row 0 -col 1 -move_dashboard_gadget -name {utilization_2} -row 1 -col 1 -move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git a/rtl/arty-a7/sdspi_testbench_behav.wcfg b/tridoracpu/sdspi_testbench_behav.wcfg similarity index 100% rename from rtl/arty-a7/sdspi_testbench_behav.wcfg rename to tridoracpu/sdspi_testbench_behav.wcfg diff --git a/tridoracpu/testbench_behav.wcfg b/tridoracpu/testbench_behav.wcfg new file mode 100644 index 0000000..26d6df1 --- /dev/null +++ b/tridoracpu/testbench_behav.wcfg @@ -0,0 +1,272 @@ + + + + + + + + + + + + + + + + + + + + + + + + seq_state[1:0] + seq_state[1:0] + UNSIGNEDDECRADIX + + + PC[15:0] + PC[15:0] + HEXRADIX + #D2691E + true + + + nPC[15:0] + nPC[15:0] + HEXRADIX + #D2691E + true + + + ins[15:0] + ins[15:0] + #D2691E + true + + + operand[15:0] + operand[15:0] + #D2691E + true + + + ins_branch + ins_branch + #D2691E + true + + + ins_cbranch + ins_cbranch + #D2691E + true + + + ins_load + ins_load + #D2691E + true + + + ins_loadc + ins_loadc + #D2691E + true + + + ins_loadi + ins_loadi + #D2691E + true + + + ins_loadim + ins_loadim + #D2691E + true + + + ins_store + ins_store + #A52A2A + true + + + ins_aluop + ins_aluop + #D2691E + true + + + aluop[3:0] + aluop[3:0] + #FFD700 + true + BINARYRADIX + + + aluop_sd[1:0] + aluop_sd[1:0] + #FFD700 + true + SIGNEDDECRADIX + + + aluop_x2y + aluop_x2y + #FFD700 + true + + + mem_addr[15:0] + mem_addr[15:0] + #DCDCDC + true + + + mem_read_enable + mem_read_enable + #E0FFFF + true + + + mem_read_data[15:0] + mem_read_data[15:0] + HEXRADIX + #E0FFFF + true + + + mem_write_enable + mem_write_enable + #E0FFFF + true + + + mem_write_data[15:0] + mem_write_data[15:0] + HEXRADIX + #E0FFFF + true + + + X[15:0] + X[15:0] + HEXRADIX + #FF0080 + true + + + nX[15:0] + nX[15:0] + HEXRADIX + #FF0080 + true + + + Y[15:0] + Y[15:0] + HEXRADIX + #FF0080 + true + + + FP[15:0] + FP[15:0] + #DCDCDC + true + HEXRADIX + + + BP[15:0] + BP[15:0] + HEXRADIX + #DCDCDC + true + + + RP[15:0] + RP[15:0] + #E0FFFF + true + + + nRP[15:0] + nRP[15:0] + #E0FFFF + true + + + ESP[5:0] + ESP[5:0] + #008080 + true + + + nESP[5:0] + nESP[5:0] + #008080 + true + + + stack_write + stack_write + #008080 + true + + + [0][15:0] + [0][15:0] + HEXRADIX + #F0E68C + true + + + [1][15:0] + [1][15:0] + HEXRADIX + #F0E68C + true + + + [2][15:0] + [2][15:0] + HEXRADIX + #F0E68C + true + + + [3][15:0] + [3][15:0] + #F0E68C + true + + + [4][15:0] + [4][15:0] + HEXRADIX + #F0E68C + true + + + [5][15:0] + [5][15:0] + HEXRADIX + #F0E68C + true + + + [6][15:0] + [6][15:0] + #F0E68C + true + + + [7][15:0] + [7][15:0] + #F0E68C + true + + diff --git a/rtl/arty-a7/testbench_behav1.wcfg b/tridoracpu/testbench_behav1.wcfg similarity index 100% rename from rtl/arty-a7/testbench_behav1.wcfg rename to tridoracpu/testbench_behav1.wcfg diff --git a/rtl/arty-a7/Arty-A7-35-Master.xdc b/tridoracpu/tridoracpu.srcs/Arty-A7-35-Master.xdc similarity index 100% rename from rtl/arty-a7/Arty-A7-35-Master.xdc rename to tridoracpu/tridoracpu.srcs/Arty-A7-35-Master.xdc diff --git a/rtl/src/bram_tdp.v b/tridoracpu/tridoracpu.srcs/bram_tdp.v similarity index 100% rename from rtl/src/bram_tdp.v rename to tridoracpu/tridoracpu.srcs/bram_tdp.v diff --git a/rtl/src/cpuclk.v b/tridoracpu/tridoracpu.srcs/cpuclk.v similarity index 100% rename from rtl/src/cpuclk.v rename to tridoracpu/tridoracpu.srcs/cpuclk.v diff --git a/rtl/src/display_clock.v b/tridoracpu/tridoracpu.srcs/display_clock.v similarity index 100% rename from rtl/src/display_clock.v rename to tridoracpu/tridoracpu.srcs/display_clock.v diff --git a/rtl/src/dram_bridge.v b/tridoracpu/tridoracpu.srcs/dram_bridge.v similarity index 100% rename from rtl/src/dram_bridge.v rename to tridoracpu/tridoracpu.srcs/dram_bridge.v diff --git a/rtl/src/fifo.v b/tridoracpu/tridoracpu.srcs/fifo.v similarity index 100% rename from rtl/src/fifo.v rename to tridoracpu/tridoracpu.srcs/fifo.v diff --git a/rtl/src/fifo_testbench.v b/tridoracpu/tridoracpu.srcs/fifo_testbench.v similarity index 100% rename from rtl/src/fifo_testbench.v rename to tridoracpu/tridoracpu.srcs/fifo_testbench.v diff --git a/rtl/src/irqctrl.v b/tridoracpu/tridoracpu.srcs/irqctrl.v similarity index 100% rename from rtl/src/irqctrl.v rename to tridoracpu/tridoracpu.srcs/irqctrl.v diff --git a/rtl/src/mem.v b/tridoracpu/tridoracpu.srcs/mem.v similarity index 100% rename from rtl/src/mem.v rename to tridoracpu/tridoracpu.srcs/mem.v diff --git a/rtl/arty-a7/mig_dram_0/mig_a.prj b/tridoracpu/tridoracpu.srcs/mig_dram_0/mig_a.prj similarity index 100% rename from rtl/arty-a7/mig_dram_0/mig_a.prj rename to tridoracpu/tridoracpu.srcs/mig_dram_0/mig_a.prj diff --git a/rtl/arty-a7/mig_dram_0/mig_b.prj b/tridoracpu/tridoracpu.srcs/mig_dram_0/mig_b.prj similarity index 100% rename from rtl/arty-a7/mig_dram_0/mig_b.prj rename to tridoracpu/tridoracpu.srcs/mig_dram_0/mig_b.prj diff --git a/rtl/src/palette.v b/tridoracpu/tridoracpu.srcs/palette.v similarity index 100% rename from rtl/src/palette.v rename to tridoracpu/tridoracpu.srcs/palette.v diff --git a/rtl/src/sdspi.v b/tridoracpu/tridoracpu.srcs/sdspi.v similarity index 100% rename from rtl/src/sdspi.v rename to tridoracpu/tridoracpu.srcs/sdspi.v diff --git a/rtl/src/sdspi_testbench.v b/tridoracpu/tridoracpu.srcs/sdspi_testbench.v similarity index 100% rename from rtl/src/sdspi_testbench.v rename to tridoracpu/tridoracpu.srcs/sdspi_testbench.v diff --git a/tridoracpu/tridoracpu.srcs/sfifo.v b/tridoracpu/tridoracpu.srcs/sfifo.v new file mode 100644 index 0000000..f5063aa --- /dev/null +++ b/tridoracpu/tridoracpu.srcs/sfifo.v @@ -0,0 +1,84 @@ +`timescale 1ns / 1ps + +// a simple fifo +module fifo #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 4)( + input wire clk, + input wire reset, + input wire wr_en, + input wire rd_en, + input wire [DATA_WIDTH-1:0] wr_data, + output wire [DATA_WIDTH-1:0] rd_data, + output wire wr_full, + output wire rd_empty + ); + + reg [DATA_WIDTH-1:0] mem [0:ADDR_WIDTH-1]; + reg [ADDR_WIDTH:0] head_x = 0; // head and tail have one extra bit + reg [ADDR_WIDTH:0] tail_x = 0; // for detecting overflows + wire [ADDR_WIDTH-1:0] head = head_x[ADDR_WIDTH-1:0]; + wire [ADDR_WIDTH-1:0] tail = tail_x[ADDR_WIDTH-1:0]; + + assign rd_data = mem[tail]; + // the fifo is full when head and tail pointer are the same + // and the extra bits differ (a wraparound occured) + assign wr_full = (head == tail) && (head_x[ADDR_WIDTH] != tail_x[ADDR_WIDTH]); + // the fifo is empty when head and tail pointer are the same + // and the extra bits are the same (no wraparound) + assign rd_empty = (head == tail) && (head_x[ADDR_WIDTH] == tail_x[ADDR_WIDTH]); + + // Writing to FIFO + always @(posedge clk) begin + if (wr_en) + begin + mem[head[ADDR_WIDTH-1:0]] <= wr_data; + // move head, possible wraparound + head_x <= head_x + 1'b1; + end + end + + // Reading from FIFO + always @(posedge clk) + begin + if (rd_en) + begin + // rd_data always has current tail data + // move tail, possible wraparound + tail <= tail + 1'b1; + end + end + + // Calculating full/empty flags, referenced from zipcpu.com + wire [c_DEPTH:0] dblnext, nxtread; + assign dblnext = wraddr + 2; + assign nxtread = rdaddr + 1'b1; + + always @(posedge i_Clock, negedge i_Reset) + + // Reset case + if (!i_Reset) + begin + // Reset output flags + fifo_full <= 1'b0; + fifo_empty <= 1'b1; + + end else casez({ i_Write_En, i_Read_En, !fifo_full, !fifo_empty }) + 4'b01?1: begin // A successful read + fifo_full <= 1'b0; + fifo_empty <= (nxtread == wraddr); + end + 4'b101?: begin // A successful write + fifo_full <= (dblnext == rdaddr); + fifo_empty <= 1'b0; + end + 4'b11?0: begin // Successful write, failed read + fifo_full <= 1'b0; + fifo_empty <= 1'b0; + end + 4'b11?1: begin // Successful read and write + fifo_full <= fifo_full; + fifo_empty <= 1'b0; + end + default: begin end + endcase + +endmodule \ No newline at end of file diff --git a/rtl/src/stack.v b/tridoracpu/tridoracpu.srcs/stack.v similarity index 100% rename from rtl/src/stack.v rename to tridoracpu/tridoracpu.srcs/stack.v diff --git a/rtl/src/stackcpu.v b/tridoracpu/tridoracpu.srcs/stackcpu.v similarity index 100% rename from rtl/src/stackcpu.v rename to tridoracpu/tridoracpu.srcs/stackcpu.v diff --git a/rtl/src/testbench.v b/tridoracpu/tridoracpu.srcs/testbench.v similarity index 100% rename from rtl/src/testbench.v rename to tridoracpu/tridoracpu.srcs/testbench.v diff --git a/rtl/src/top.v b/tridoracpu/tridoracpu.srcs/top.v similarity index 100% rename from rtl/src/top.v rename to tridoracpu/tridoracpu.srcs/top.v diff --git a/rtl/src/uart.v b/tridoracpu/tridoracpu.srcs/uart.v similarity index 100% rename from rtl/src/uart.v rename to tridoracpu/tridoracpu.srcs/uart.v diff --git a/rtl/src/uart_tb.v b/tridoracpu/tridoracpu.srcs/uart_tb.v similarity index 100% rename from rtl/src/uart_tb.v rename to tridoracpu/tridoracpu.srcs/uart_tb.v diff --git a/rtl/src/vgafb.v b/tridoracpu/tridoracpu.srcs/vgafb.v similarity index 100% rename from rtl/src/vgafb.v rename to tridoracpu/tridoracpu.srcs/vgafb.v diff --git a/tridoracpu/tridoracpu.xpr b/tridoracpu/tridoracpu.xpr new file mode 100644 index 0000000..5e4a64f --- /dev/null +++ b/tridoracpu/tridoracpu.xpr @@ -0,0 +1,417 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + +