import Vivado project, rearrange Verilog sources
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29 changed files with 789 additions and 742 deletions
372
tridoracpu/tridoracpu.srcs/sdspi.v
Normal file
372
tridoracpu/tridoracpu.srcs/sdspi.v
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`timescale 1ns / 1ps
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// Every spi_clk_div cpu clock cycles the spi clock line is inverted.
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// So a spi clock cycle is 2*spi_clk_div cpu clock cycles.
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// spi_clk_count counts the cpu cycles from spi_clk_div down to zero.
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// The resulting spi clock frequency is:
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// (cpu clock freq) / ((sclk_count + 1) * 2)
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// So for a 83.33 MHz cpu clock, we get
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// spi_clk_div = 10: 83.333 / 22 = 3.788 MHz
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// spi_clk_div = 124: 83.333 / 250 = 333.33 KHz
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module sdspi(
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input wire clk, // bus clock
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input wire reset,
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input wire[7:0] tx_data, // data to transmit
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output wire[7:0] rx_data, // data received
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output wire tx_ready, // ready to write a data byte
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output wire tx_empty, // transmitter fifo is empty
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output wire rx_avail, // a byte has been received
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output wire rx_ovr, // receiver overrun
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input wire tx_write, // write strobe
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input wire rx_read, // read strobe (clears rx_ovr)
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output wire card_detect, // true is card is present
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output wire card_changed, // card_detect signal has changed
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output wire card_busy, // card is busy (MISO/DO is 0)
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input wire ctrl_write, // set the following flags
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input wire rx_filter_en, // set to discard received $FF bytes
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input wire txrx_en, // enable transmitter and receiver
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input wire spiclk_f_en, // enable spi clock without cs
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input wire spiclk_div_wr, // set clock divider via tx_data
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// PMOD connections
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output wire sd_cs_n,
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output reg sd_mosi,
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input wire sd_miso,
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output wire sd_sck,
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input wire sd_cd
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);
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localparam CLKPHASE_0A = 2'b00;
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localparam CLKPHASE_0B = 2'b01;
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localparam CLKPHASE_1A = 2'b10;
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localparam CLKPHASE_1B = 2'b11;
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reg [1:0] clk_phase;
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reg xcvr_on; // if turned off, the rest of the current byte
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// will still transmitted, and until then "running"
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// will be 1
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(* KEEP *)
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reg running; // transmitting/receiving a byte (maybe a dummy byte)
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(* KEEP *) reg [3:0] xcvr_bitcount; // number of bits left of the current byte
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reg [7:0] tx_shifter;
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wire tx_fifo_wr_en;
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reg tx_fifo_rd_en;
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wire tx_fifo_full;
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wire tx_fifo_empty;
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wire [7:0] tx_fifo_out;
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reg [7:0] rx_shifter;
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reg rx_filter;
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reg rx_fifo_wr_en;
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wire rx_fifo_rd_en;
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wire rx_fifo_full;
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wire rx_fifo_empty;
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wire [7:0] rx_fifo_out;
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reg rx_bit_recvd; // this flag signals a received bit
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reg rx_overrun; // byte received when rx fifo is full
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reg c_changed;
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reg c_cs;
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reg spi_clk; // the spi clock signal
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reg spi_clk_on; // enable clock, either via init mode or by xcvr_on
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reg spi_clk_f_on; // init clock mode, i.e. start clock but no tx/rx
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reg [6:0] spi_clk_count; // counting cpu clock ticks
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reg [6:0] spi_clk_div; // tick counter for spi clock phases
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wire spi_clk_count_z = (spi_clk_count == 7'b0);
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reg hphase_start; // start of a spi clock half-phase
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assign tx_ready = !tx_fifo_full;
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assign tx_empty = tx_fifo_empty;
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assign rx_avail = !rx_fifo_empty;
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assign rx_ovr = rx_overrun;
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assign rx_data = rx_fifo_out;
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assign card_busy = (sd_miso == 0);
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assign card_changed = c_changed;
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assign sd_sck = spi_clk;
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assign sd_cs_n = ~c_cs;
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assign card_detect = sd_cd;
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fifo #(.ADDR_WIDTH(4)) tx_fifo(clk, reset,
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tx_fifo_wr_en, tx_fifo_rd_en,
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tx_data, tx_fifo_out,
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tx_fifo_full,
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tx_fifo_empty
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);
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fifo #(.ADDR_WIDTH(8)) rx_fifo(clk, reset,
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rx_fifo_wr_en, rx_fifo_rd_en,
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rx_shifter, rx_fifo_out,
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rx_fifo_full,
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rx_fifo_empty
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);
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// spi clock
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always @(posedge clk)
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begin
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if(reset)
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begin
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spi_clk <= 1; // CLK is high when inactive
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spi_clk_on <= 0;
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spi_clk_count <= 0;
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end
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else if(spi_clk_on)
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begin
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// set spi_clk at start of every half-phase
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if(hphase_start)
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case(clk_phase)
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CLKPHASE_0A: spi_clk <= 1'b0;
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CLKPHASE_0B: spi_clk <= 1'b0;
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CLKPHASE_1A: spi_clk <= 1'b1;
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CLKPHASE_1B: spi_clk <= 1'b1;
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endcase
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if(spi_clk_count_z)
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begin
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spi_clk_count <= spi_clk_div;
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clk_phase <= clk_phase + 2'b1;
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end
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else
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spi_clk_count <= spi_clk_count - 7'd1;
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end
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// start the clock if needed
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if( (spi_clk_on == 0) && (running || spi_clk_f_on))
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begin
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spi_clk_on <= 1;
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spi_clk_count <= spi_clk_div;
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clk_phase <= CLKPHASE_1A;
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end
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// turn off the clock if transceiver not running
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// and the force-clock-on flag is not set
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if( (spi_clk_on == 1) && (!running && !spi_clk_f_on))
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begin
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spi_clk_on <= 0;
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spi_clk <= 1'b1;
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end
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end
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// half-phase-start flag trails spi_clk_count_z by one tick
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always @(posedge clk)
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begin
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if(reset)
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hphase_start <= 0;
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else
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hphase_start <= spi_clk_on && spi_clk_count_z;
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end
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// handle the force clock enable flag
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always @(posedge clk)
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begin
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if (reset)
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spi_clk_f_on <= 0;
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else
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if (ctrl_write)
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spi_clk_f_on <= spiclk_f_en;
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end
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// clock divider
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always @(posedge clk)
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begin
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if (spiclk_div_wr) spi_clk_div <= tx_data[6:0];
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end
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// card_changed flag
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always @(posedge clk)
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begin
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if(sd_cd)
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c_changed <= 1;
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else if(ctrl_write || reset)
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c_changed <= 0;
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end
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// cs signal
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always @(posedge clk)
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begin
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if(hphase_start && clk_phase == CLKPHASE_0A || !running)
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c_cs <= running;
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end
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// transmitter
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always @(posedge clk)
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begin
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if(reset)
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begin
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// ???? we start the bitcount at 1 because we start
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// at the second clock phase where the bitcount
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// is decremented and the next byte gets loaded
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xcvr_bitcount <= 0;
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tx_shifter <= 8'b1;
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xcvr_on <= 0;
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sd_mosi <= 1;
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tx_fifo_rd_en <= 0;
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end
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else
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begin
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// handle a control write to disable the transceiver
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if(ctrl_write && !txrx_en && xcvr_on)
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xcvr_on <= 0;
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// a byte might still be in transit, so
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// we do not disable the transceiver
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// immediately (see "handle running status" below)
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else
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// handle control write to enable the transceiver
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if(ctrl_write && txrx_en && !running)
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begin
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xcvr_on <= 1;
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xcvr_bitcount <= 0;
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// next clock phase must be 1B when starting the transceiver,
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// so that the first byte is loaded into the shifter then
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tx_shifter <= 8'b11111111;
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// in case the transceiver is enabled, but no data is in the fifo,
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// initialize the shifter with $FF
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end
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else
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// handle clock phases
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if (running)
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begin
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if(hphase_start)
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case(clk_phase)
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// set mosi signal at start of clock pulse
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CLKPHASE_0A: sd_mosi <= tx_shifter[7];
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CLKPHASE_0B: ;
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CLKPHASE_1A: begin // shift at rising clock
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tx_shifter <= tx_shifter << 1;
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xcvr_bitcount <= xcvr_bitcount - 1;
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end
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CLKPHASE_1B: begin // in the middle of the high clock pulse,
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// fetch the next byte if there are no bits
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// left in the shift register
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if (xcvr_bitcount == 0)
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begin
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if(!tx_fifo_empty)
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begin
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tx_shifter <= tx_fifo_out;
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tx_fifo_rd_en <= 1;
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end
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else
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tx_shifter <= 8'b11111111;
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xcvr_bitcount <= 8;
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end
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else
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tx_fifo_rd_en <= 0;
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end
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endcase
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else
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tx_fifo_rd_en <= 0;
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end
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end
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end
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// handle data write
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assign tx_fifo_wr_en = tx_write && !tx_fifo_full;
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// Enable fifo read signal if fifo is not empty.
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// The data at the fifo tail is always available at
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// rx_data, the read signal just moves the tail pointer
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// forward.
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assign rx_fifo_rd_en = rx_read && !rx_fifo_empty;
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// receiver
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always @(posedge clk)
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begin
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if(reset)
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begin
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rx_bit_recvd <= 0;
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rx_shifter <= 8'b11111111;
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rx_fifo_wr_en <= 0;
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rx_filter <= 0;
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rx_overrun <= 0;
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end
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else
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begin
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// handle a control write
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if(ctrl_write)
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begin
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rx_filter <= rx_filter_en;
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rx_overrun <= 0;
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if(txrx_en && !running)
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rx_shifter <= 8'b0;
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end
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if (running && hphase_start)
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case(clk_phase)
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CLKPHASE_0A: ;
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CLKPHASE_0B: ;
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CLKPHASE_1A: ;
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CLKPHASE_1B: begin // in the middle of the high clock pulse,
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// sample MISO and put into shift register
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// and shift at the same time
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rx_shifter <= { rx_shifter[6:0],sd_miso};
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rx_bit_recvd <= 1;
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end
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endcase
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if (rx_bit_recvd && !sd_cs_n && clk_phase == CLKPHASE_1B)
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begin
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rx_bit_recvd <= 0;
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// if a complete byte was received, bitcount will be
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// 8 because the transmitter has already loaded the next byte
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// at this half-phase
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if (xcvr_bitcount == 8)
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begin
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// discard $FF bytes if filter is enabled
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if(!rx_filter || rx_shifter != 8'b11111111)
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begin
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if(rx_fifo_full) // discard received byte if fifo is full
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rx_overrun <= 1; // and set overrun flag
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else
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rx_fifo_wr_en <= 1; // otherwise, enable fifo write strobe,
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// fifo will take data from rx_shifter
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end
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// turn off filter if a byte != $FF was received
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if (rx_filter && rx_shifter != 8'b11111111)
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rx_filter <= 0;
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end
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end
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else
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rx_fifo_wr_en <= 0;
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end
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end
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// handle running status
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// (especially keep transmitter running when there are still bits left to be
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// transmitted)
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always@(posedge clk)
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begin
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if (reset)
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running <= 0;
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else
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begin
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// if we want to turn the transceiver on, set running flag
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if (!running && xcvr_on)
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running <= 1;
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// when running and a byte has been transmitted,
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// check if we should turn the transceiver off
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if (running && hphase_start && xcvr_bitcount==0)
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if(clk_phase == CLKPHASE_1B)
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if (!xcvr_on)
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running <= 0;
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end
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end
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endmodule
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