import Vivado project, rearrange Verilog sources
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29 changed files with 789 additions and 742 deletions
88
tridoracpu/testbench_behav1.wcfg
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88
tridoracpu/testbench_behav1.wcfg
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<?xml version="1.0" encoding="UTF-8"?>
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<wave_config>
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<wave_state>
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</wave_state>
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<db_ref_list>
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<db_ref path="testbench_behav.wdb" id="1">
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<top_modules>
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<top_module name="glbl" />
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<top_module name="testbench" />
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</top_modules>
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</db_ref>
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</db_ref_list>
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<zoom_setting>
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<ZoomStartTime time="3880386400fs"></ZoomStartTime>
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<ZoomEndTime time="4023922720fs"></ZoomEndTime>
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<Cursor1Time time="4000000000fs"></Cursor1Time>
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</zoom_setting>
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<column_width_setting>
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<NameColumnWidth column_width="209"></NameColumnWidth>
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<ValueColumnWidth column_width="90"></ValueColumnWidth>
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</column_width_setting>
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<WVObjectSize size="16" />
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<wvobject fp_name="/testbench/clk" type="logic">
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<obj_property name="ElementShortName">clk</obj_property>
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<obj_property name="ObjectShortName">clk</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/addr" type="array">
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<obj_property name="ElementShortName">addr[31:0]</obj_property>
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<obj_property name="ObjectShortName">addr[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/data_in" type="array">
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<obj_property name="ElementShortName">data_in[31:0]</obj_property>
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<obj_property name="ObjectShortName">data_in[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/data_out" type="array">
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<obj_property name="ElementShortName">data_out[31:0]</obj_property>
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<obj_property name="ObjectShortName">data_out[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/seq_state" type="array">
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<obj_property name="ElementShortName">seq_state[1:0]</obj_property>
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<obj_property name="ObjectShortName">seq_state[1:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/PC" type="array">
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<obj_property name="ElementShortName">PC[31:0]</obj_property>
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<obj_property name="ObjectShortName">PC[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/nPC" type="array">
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<obj_property name="ElementShortName">nPC[31:0]</obj_property>
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<obj_property name="ObjectShortName">nPC[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/ins" type="array">
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<obj_property name="ElementShortName">ins[15:0]</obj_property>
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<obj_property name="ObjectShortName">ins[15:0]</obj_property>
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<obj_property name="Radix">BINARYRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/ins_branch" type="logic">
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<obj_property name="ElementShortName">ins_branch</obj_property>
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<obj_property name="ObjectShortName">ins_branch</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/ins_loadrel" type="logic">
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<obj_property name="ElementShortName">ins_loadrel</obj_property>
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<obj_property name="ObjectShortName">ins_loadrel</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/X" type="array">
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<obj_property name="ElementShortName">X[31:0]</obj_property>
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<obj_property name="ObjectShortName">X[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/nX" type="array">
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<obj_property name="ElementShortName">nX[31:0]</obj_property>
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<obj_property name="ObjectShortName">nX[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/FP" type="array">
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<obj_property name="ElementShortName">FP[31:0]</obj_property>
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<obj_property name="ObjectShortName">FP[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/pc_next_ins" type="array">
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<obj_property name="ElementShortName">pc_next_ins[31:0]</obj_property>
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<obj_property name="ObjectShortName">pc_next_ins[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/mem_wait" type="logic">
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<obj_property name="ElementShortName">mem_wait</obj_property>
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<obj_property name="ObjectShortName">mem_wait</obj_property>
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</wvobject>
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<wvobject fp_name="/testbench/top0/cpu0/ins_buf" type="array">
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<obj_property name="ElementShortName">ins_buf[15:0]</obj_property>
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<obj_property name="ObjectShortName">ins_buf[15:0]</obj_property>
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</wvobject>
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</wave_config>
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