slederer/Tridora-CPU
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import Vivado project, rearrange Verilog sources

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slederer 2024-09-27 22:13:23 +02:00
parent 18b95b6bb6
commit a441e7e042
29 changed files with 789 additions and 742 deletions
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.gitignore vendored
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@ -2,6 +2,7 @@ pcomp/*.s
progs/*.s
tests/*.s
examples/*.s
!runtime.s
*.o
*.exe
*.bin
@ -21,14 +22,18 @@ sine.pas
graph1.pas
graph2.pas
chase.pas
!runtime.s
**/tridoracpu.*/
rtl/arty-a7/mig_dram_0/_tmp/*
rtl/arty-a7/mig_dram_0/doc/*
rtl/arty-a7/mig_dram_0/mig_dram_0*
rtl/arty-a7/mig_dram_0/xil_txt.*
rtl/arty-a7/mig_dram_0/*.veo
rtl/arty-a7/mig_dram_0/*.tcl
rtl/arty-a7/mig_dram_0/*.xml
rtl/arty-a7/mig_dram_0/*.v
rtl/arty-a7/mig_dram_0/*.vhdl
**/tridoracpu.cache/
**/tridoracpu.hw/
**/tridoracpu.ip_user_files/
**/tridoracpu.runs/
*.log
*.jou
**/mig_dram_0/_tmp/*
**/mig_dram_0/doc/*
**/mig_dram_0/mig_dram_0*
**/mig_dram_0/xil_txt.*
**/mig_dram_0/*.veo
**/mig_dram_0/*.tcl
**/mig_dram_0/*.xml
**/mig_dram_0/*.v
**/mig_dram_0/*.vhdl