slederer/Tridora-CPU
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages 3 Wiki Activity Actions

lib,examples: changes for new register address mapping

Browse source
This commit is contained in:
slederer 2026-01-28 01:15:16 +01:00
parent 248c9ae919
commit 937369f60b
6 changed files with 25 additions and 28 deletions
Download patch file Download diff file Expand all files Collapse all files

10
examples/fastfire.s
View file

@ -123,11 +123,11 @@ FF_EXIT:
; framebuffer controller registers ; framebuffer controller registers
.EQU FB_RA $900 .EQU FB_RA $900
.EQU FB_WA $901 .EQU FB_WA $904
.EQU FB_IO $902 .EQU FB_IO $908
.EQU FB_PS $903 .EQU FB_PS $90C
.EQU FB_PD $904 .EQU FB_PD $910
.EQU FB_CTL $905 .EQU FB_CTL $914
.EQU WORDS_PER_LINE 80 .EQU WORDS_PER_LINE 80
; fire width in vmem words (strict left-to-right evaluation) ; fire width in vmem words (strict left-to-right evaluation)

10
examples/sprites.s
View file

@ -3,9 +3,9 @@
.EQU WORDS_PER_LINE 80 .EQU WORDS_PER_LINE 80
.EQU FB_RA $900 .EQU FB_RA $900
.EQU FB_WA $901 .EQU FB_WA $904
.EQU FB_IO $902 .EQU FB_IO $908
.EQU FB_PS $903 .EQU FB_PS $90C
; calculate mask for a word of pixels ; calculate mask for a word of pixels
; args: word of pixels with four bits per pixel ; args: word of pixels with four bits per pixel
@ -95,7 +95,7 @@ PS_LOOP1:
; in the vga controller ; in the vga controller
LOADC FB_RA ; read address register LOADC FB_RA ; read address register
LOAD PS_VMEM_ADDR LOAD PS_VMEM_ADDR
STOREI 1 ; use autoincrement to get to the next register STOREI 4 ; use autoincrement to get to the next register
LOAD PS_VMEM_ADDR LOAD PS_VMEM_ADDR
STOREI STOREI
DROP DROP
@ -322,7 +322,7 @@ UD_S_L1:
; store vmem offset into write addr reg ; store vmem offset into write addr reg
LOADCP FB_WA LOADCP FB_WA
LOAD UD_S_OFFSET LOAD UD_S_OFFSET
STOREI 1 ; ugly but fast: reuse addr STOREI 4 ; ugly but fast: reuse addr
; with postincrement to ; with postincrement to
; get to FB_IO for STOREI below ; get to FB_IO for STOREI below

10
lib/corelib.s
View file

@ -701,11 +701,11 @@ CMPWORDS_XT2:
; --------- Graphics Library --------------- ; --------- Graphics Library ---------------
; vga controller registers ; vga controller registers
.EQU FB_RA $900 .EQU FB_RA $900
.EQU FB_WA $901 .EQU FB_WA $904
.EQU FB_IO $902 .EQU FB_IO $908
.EQU FB_PS $903 .EQU FB_PS $90C
.EQU FB_PD $904 .EQU FB_PD $910
.EQU FB_CTL $905 .EQU FB_CTL $914
; set a pixel in fb memory ; set a pixel in fb memory
; parameters: x,y - coordinates ; parameters: x,y - coordinates
PUTPIXEL_1BPP: PUTPIXEL_1BPP:

10
lib/pcmaudio.s
View file

@ -11,9 +11,9 @@ START_PCMAUDIO:
LOADCP _DIV LOADCP _DIV
CALL CALL
LOADC AUDIO_BASE + 1 LOADC AUDIO_BASE + 4
SWAP ; put clock divider on ToS SWAP ; put clock divider on ToS
STOREI 1 STOREI 4
LOADCP 32768 ; set amplitude to biased 0 LOADCP 32768 ; set amplitude to biased 0
STOREI STOREI
DROP DROP
@ -95,7 +95,7 @@ PLAY1_L0:
AND AND
CBRANCH.NZ PLAY1_L0 ; loop if fifo is full CBRANCH.NZ PLAY1_L0 ; loop if fifo is full
LOADC AUDIO_BASE+2 ; store amplitude value LOADC AUDIO_BASE+8 ; store amplitude value
SWAP SWAP
STOREI STOREI
DROP DROP
@ -207,7 +207,7 @@ SMPLQ_I_B:
LOADCP $FFFF LOADCP $FFFF
AND AND
LOADC AUDIO_BASE+2 LOADC AUDIO_BASE+8
SWAP SWAP
STOREI ; write sample, keep addr STOREI ; write sample, keep addr
@ -281,7 +281,7 @@ SMPLQ_I_END1:
DROP DROP
; set amplitude out to zero (biased) ; set amplitude out to zero (biased)
LOADC AUDIO_BASE+2 LOADC AUDIO_BASE+8
LOADCP 32768 LOADCP 32768
STOREI STOREI
DROP DROP

10
tridoracpu/tridoracpu.srcs/vgafb.v
View file

@ -132,9 +132,9 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
`ifdef ENABLE_FB_ACCEL `ifdef ENABLE_FB_ACCEL
localparam REG_SHIFTER = 6; localparam REG_SHIFTER = 6;
localparam REG_SHIFTCOUNT = 7; localparam REG_SHIFTCOUNT = 7;
localparam REG_SHIFTERM = 9; localparam REG_SHIFTERM = 8;
localparam REG_SHIFTERSP = 10; localparam REG_SHIFTERSP = 09;
localparam REG_MASKGEN = 11; localparam REG_MASKGEN = 10;
`endif `endif
localparam COLOR_WIDTH = 12; localparam COLOR_WIDTH = 12;
@ -325,19 +325,15 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
always @(posedge cpu_clk) always @(posedge cpu_clk)
begin begin
if (acc_start_shift) if (acc_start_shift)
begin
acc_shifter_out <= {acc_shifter_in, {VMEM_DATA_WIDTH{1'b0}}} >> acc_shift_count; acc_shifter_out <= {acc_shifter_in, {VMEM_DATA_WIDTH{1'b0}}} >> acc_shift_count;
end end
end
// mask register // mask register
always @(posedge cpu_clk) always @(posedge cpu_clk)
begin begin
if (wr_en && reg_sel == REG_MASKGEN) if (wr_en && reg_sel == REG_MASKGEN)
begin
acc_mask_in <= wr_data; acc_mask_in <= wr_data;
end end
end
assign acc_mask_out = { assign acc_mask_out = {
{4{|{acc_mask_in[31:28]}}}, {4{|{acc_mask_in[31:28]}}},

3
tridoracpu/tridoracpu.xpr
View file

@ -376,7 +376,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/> <Step Id="init_design"/>
@ -389,6 +389,7 @@
<Step Id="post_route_phys_opt_design"/> <Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/> <Step Id="write_bitstream"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>