docs: add UART documentation
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## Documentation
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## Documentation
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- [Instruction Reference](doc/tridoracpu.md)
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- [Instruction Reference](doc/tridoracpu.md)
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- [Memory Layout](doc/mem.md)
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- [Memory Layout](doc/mem.md)
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- [UART](doc/uart.md)
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- [SD-Card controller](doc/spisd.md)
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- [SD-Card controller](doc/spisd.md)
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- [VGA controller](doc/vga.md)
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- [VGA controller](doc/vga.md)
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More documentation is coming as time permits.
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More documentation is coming, as time permits.
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doc/uart.md
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46
doc/uart.md
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# UART
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The UART a single register at address $900.
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It uses a fixed serial configuration of 115200 bps, 8 data bits, 1 stop bit, no parity.
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## Reading the UART register
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|_bit_ |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|u |u |u |u |u |u |u |u |u |u |u |u |u |u |u |u |
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|_bit_ |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|u |u |u |u |u |u |A |B |d |d |d |d |d |d | d | d |
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|Bitfields|Description|
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|---------|-----------|
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| _A_ | data available, at least one byte has been received
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| _B_ | TX busy, a byte is being transmitted and no data can be written
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| _d_ | 8 data bits
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| _u_ | unused
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## Writing the UART register
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|_bit_ |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|u |u |u |u |u |u |u |u |u |u |u |u |u |u |u |u |
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|_bit_ |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
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|- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |- |
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|_Value_|u |u |u |u |u |T |C |u |d |d |d |d |d |d | d | d |
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|Bitfields|Description|
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|---------|-----------|
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| _T_ | transmit enable, writes a data byte
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| _C_ | clear receiver, acknowledges a received byte
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| _d_ | 8 data bits
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| _u_ | unused
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## Notes
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A 16 byte FIFO is used when receiving data.
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When reading data, each byte needs to be acknowledged by writing the _C_ flag to the UART register.
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When the FIFO is empty, the _A_ flag in the UART register will be 0.
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