Makefile and constraints for GateMateA1-EVB board

tridoracpu/Makefile

@@ -0,0 +1,56 @@
+SRCDIR := tridoracpu.srcs
+TOOLCHAIN := $(CC_TOOL)
+
+YOSYS = $(TOOLCHAIN)/bin/yosys/yosys$(EXE)
+PNR   = $(TOOLCHAIN)/bin/p_r/p_r$(EXE)
+OFL   = openFPGAloader
+
+IVLFLAGS = -g2012 -gspecify -Ttyp
+OFLFLAGS = --cable dirtyJtag
+
+TOP      = top
+CONSTR   = $(SRCDIR)/GateMateA1-EVB.ccf
+PNRFLAGS += -ccf $(CONSTR) -cCP
+
+SYNTHFILE = build/$(TOP)_synth.v
+
+BITSTREAM = build/$(TOP)_00.cfg.bit
+
+srcs = \
+    $(SRCDIR)/bram_tdp.v \
+    $(SRCDIR)/dram_bridge.v \
+    $(SRCDIR)/fifo.v \
+    $(SRCDIR)/irqctrl.v \
+    $(SRCDIR)/mem.v \
+    $(SRCDIR)/palette.v \
+    $(SRCDIR)/sdspi.v \
+    $(SRCDIR)/stackcpu.v \
+    $(SRCDIR)/stack.v \
+    $(SRCDIR)/top.v \
+    $(SRCDIR)/uart.v \
+    $(SRCDIR)/vgafb.v
+
+#srcs += $(SRCDIR)/ccgma1_clocks.v 
+
+all: build synth impl
+clean:
+	rm -rf build
+
+.PHONY: all clean
+
+build:
+	mkdir $@
+
+synth: $(SYNTHFILE)
+impl: $(BITSTREAM)
+
+
+$(SYNTHFILE): $(srcs)
+	$(YOSYS) -ql build/synth.log -p 'read -sv $(srcs); synth_gatemate -top $(TOP) -nomx8 -vlog $(SYNTHFILE)'
+
+$(BITSTREAM): $(SYNTHFILE)
+	$(PNR) -v -i build/$(SYNTHFILE) -o $(TOP) $(PNRFLAGS) >build/$@.log
+
+prog: $(BITSTREAM)
+	$(OFL) $(OFLFLAGS) --bitstream $(BITSTREAM)
+