diff --git a/tridoracpu/Makefile b/tridoracpu/Makefile new file mode 100644 index 0000000..96fc30f --- /dev/null +++ b/tridoracpu/Makefile @@ -0,0 +1,56 @@ +SRCDIR := tridoracpu.srcs +TOOLCHAIN := $(CC_TOOL) + +YOSYS = $(TOOLCHAIN)/bin/yosys/yosys$(EXE) +PNR = $(TOOLCHAIN)/bin/p_r/p_r$(EXE) +OFL = openFPGAloader + +IVLFLAGS = -g2012 -gspecify -Ttyp +OFLFLAGS = --cable dirtyJtag + +TOP = top +CONSTR = $(SRCDIR)/GateMateA1-EVB.ccf +PNRFLAGS += -ccf $(CONSTR) -cCP + +SYNTHFILE = build/$(TOP)_synth.v + +BITSTREAM = build/$(TOP)_00.cfg.bit + +srcs = \ + $(SRCDIR)/bram_tdp.v \ + $(SRCDIR)/dram_bridge.v \ + $(SRCDIR)/fifo.v \ + $(SRCDIR)/irqctrl.v \ + $(SRCDIR)/mem.v \ + $(SRCDIR)/palette.v \ + $(SRCDIR)/sdspi.v \ + $(SRCDIR)/stackcpu.v \ + $(SRCDIR)/stack.v \ + $(SRCDIR)/top.v \ + $(SRCDIR)/uart.v \ + $(SRCDIR)/vgafb.v + +#srcs += $(SRCDIR)/ccgma1_clocks.v + +all: build synth impl +clean: + rm -rf build + +.PHONY: all clean + +build: + mkdir $@ + +synth: $(SYNTHFILE) +impl: $(BITSTREAM) + + +$(SYNTHFILE): $(srcs) + $(YOSYS) -ql build/synth.log -p 'read -sv $(srcs); synth_gatemate -top $(TOP) -nomx8 -vlog $(SYNTHFILE)' + +$(BITSTREAM): $(SYNTHFILE) + $(PNR) -v -i build/$(SYNTHFILE) -o $(TOP) $(PNRFLAGS) >build/$@.log + +prog: $(BITSTREAM) + $(OFL) $(OFLFLAGS) --bitstream $(BITSTREAM) + diff --git a/tridoracpu/tridoracpu.srcs/GateMateA1-EVB.ccf b/tridoracpu/tridoracpu.srcs/GateMateA1-EVB.ccf new file mode 100644 index 0000000..27a4a46 --- /dev/null +++ b/tridoracpu/tridoracpu.srcs/GateMateA1-EVB.ccf @@ -0,0 +1,373 @@ +#======================================================================== +# openCologne * NLnet-sponsored open-source design ware for GateMate +#------------------------------------------------------------------------ +# Copyright (C) 2024 Chili.CHIPS*ba +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# https://opensource.org/license/bsd-3-clause +#------------------------------------------------------------------------ +# Description: +# Gatemate E1 evaluation board hardware pin constraints +# file: GateMateA1-EVB.ccf +## file: GateMateA1-EVB.ccf +## +## Gatemate A1-EVB Olimex board hardware pin constraints +## ####################################################### +# Format: +# "" Loc = "" | ; +# Net "" Loc = "" | ; +# +# Additional constraints can be appended using the pipe symbol. +# Files are read line by line. Text after the hash symbol is ignored. +# +# Available pin directions: +# +# Pin_in +# defines an input pin +# Pin_out +# defines an output pin +# Pin_inout +# defines a bidirectional pin +# +# Available pin constraints: +# +# SCHMITT_TRIGGER={true,false} +# enables or disables schmitt trigger (hysteresis) option +# PULLUP={true,false} +# enables or disables I/O pullup resistor of nominal 50kOhm +# PULLDOWN={true,false} +# enables or disables I/O pulldown resistor of nominal 50kOhm +# KEEPER={true,false} +# enables or disables I/O keeper option +# SLEW={slow,fast} +# sets slew rate to slow or fast +# DRIVE={3,6,9,12} +# sets output drive strength to 3mA..12mA +# DELAY_OBF={0..15} +# adds an additional delay of n * nominal 50ps to output signal +# DELAY_IBF={0..15} +# adds an additional delay of n * nominal 50ps to input signal +# FF_IBF={true,false} +# enables or disables placing of FF in input buffer, if possible +# FF_OBF={true,false} +# enables or disables placing of FF in output buffer, if possible +# LVDS_BOOST={true,false} +# enables increased LVDS output current of 6.4mA (default: 3.2mA) +# LVDS_TERM={true,false} +# enables on-chip LVDS termination resistor of nominal 100Ohm, in output mode only +# +# Global IO constraints can be set with the default_GPIO statement. It can be +# overwritten by individual settings for specific GPIOs, e.g.: +# default_GPIO | DRIVE=3; # sets all output strengths to 3mA, unless overwritten +#======================================================================== +# GPIO Configuration - Free Bank Selectable Voltage +# Bank Selectable VDD 1.2V/1.8V/2.5V/User PWR_Supply +#======================================================================== + +# Depending on how you turn the Olimex Board, the orientation of the pins is flipped +# If you turn the board so that you can read the Olimex logo and the VGA Port is to the left then the upper row is GND, NA_B.. +# And the lower row is VDD_NA, NA_A... from left to right +# +# If you turn the board so that the VGA Port is pointing up, then the VDD_NA, NA_A pins are to the left, like on the picture of the extension below +# This is the case for the Bank_NA1, Bank_NB1 and Bank_EB1 + +#======================================================================== +# Bank NA1 +#======================================================================== + +# Upper Row +# TOP LEFT PIN IS GND +Net "NA_B0" Loc = "IO_NA_B0"; +Net "NA_B1" Loc = "IO_NA_B1"; +Net "NA_B2" Loc = "IO_NA_B2"; +Net "NA_B3" Loc = "IO_NA_B3"; # Bank_NA1 +Net "NA_B4" Loc = "IO_NA_B4"; # ____________ +Net "NA_B5" Loc = "IO_NA_B5"; # VDD_NA ------- | 1 2 | -------- GND +Net "NA_B6" Loc = "IO_NA_B6"; # NA_A0 ------- | 3 4 | -------- NA_B0 +Net "NA_B7" Loc = "IO_NA_B7"; # NA_A1 ------- | 5 6 | -------- NA_B1 +Net "NA_B8" Loc = "IO_NA_B8"; # NA_A2 ------- | 7 8 | -------- NA_B2 +# ------------------------- # # NA_A3 ------- | 9 10 | -------- NA_B3 +# Lower Row # NA_A4 ------- | 11 12 | -------- NA_B4 +# BOTTOM LEFT PIN IS VDD # NA_A5 ------- | 13 14 | -------- NA_B5 +Net "NA_A0" Loc = "IO_NA_A0"; # NA_A6 ------- | 15 16 | -------- NA_B6 +Net "NA_A1" Loc = "IO_NA_A1"; # NA_A7 ------- | 17 18 | -------- NA_B7 +Net "NA_A2" Loc = "IO_NA_A2"; # NA_A8 ------- | 19 20 | -------- NA_B8 +Net "NA_A3" Loc = "IO_NA_A3"; # ____________ +Net "NA_A4" Loc = "IO_NA_A4"; +Net "NA_A5" Loc = "IO_NA_A5"; +Net "NA_A6" Loc = "IO_NA_A6"; +Net "NA_A7" Loc = "IO_NA_A7"; +Net "NA_A8" Loc = "IO_NA_A8"; + +#======================================================================== +# Bank NB1 +#======================================================================== + +# Upper Row +# TOP LEFT PIN IS GND +Net "NB_B0" Loc = "IO_NB_B0"; +Net "NB_B1" Loc = "IO_NB_B1"; +Net "NB_B2" Loc = "IO_NB_B2"; +Net "NB_B3" Loc = "IO_NB_B3"; # Bank_NB1 +Net "NB_B4" Loc = "IO_NB_B4"; # ____________ +Net "NB_B5" Loc = "IO_NB_B5"; # VDD_NA ------- | 1 2 | -------- GND +Net "NB_B6" Loc = "IO_NB_B6"; # NB_A0 ------- | 3 4 | -------- NB_B0 +Net "NB_B7" Loc = "IO_NB_B7"; # NB_A1 ------- | 5 6 | -------- NB_B1 +Net "NB_B8" Loc = "IO_NB_B8"; # NB_A2 ------- | 7 8 | -------- NB_B2 +# --------------------------# # NB_A3 ------- | 9 10 | -------- NB_B3 +# Lower Row # NB_A4 ------- | 11 12 | -------- NB_B4 +# BOTTOM LEFT PIN IS VDD # NB_A5 ------- | 13 14 | -------- NB_B5 +Net "NB_A0" Loc = "IO_NB_A0"; # NB_A6 ------- | 15 16 | -------- NB_B6 +Net "NB_A1" Loc = "IO_NB_A1"; # NB_A7 ------- | 17 18 | -------- NB_B7 +Net "NB_A2" Loc = "IO_NB_A2"; # NB_A8 ------- | 19 20 | -------- NB_B8 +Net "NB_A3" Loc = "IO_NB_A3"; # ____________ +Net "NB_A4" Loc = "IO_NB_A4"; +Net "NB_A5" Loc = "IO_NB_A5"; +Net "NB_A6" Loc = "IO_NB_A6"; +Net "NB_A7" Loc = "IO_NB_A7"; +Net "NB_A8" Loc = "IO_NB_A8"; + +#======================================================================== +# BANK_EB1 +#======================================================================== + +# Upper Row +# TOP LEFT PIN IS GND +Net "EB_B0" Loc = "IO_EB_B0"; +Net "EB_B1" Loc = "IO_EB_B1"; +Net "EB_B2" Loc = "IO_EB_B2"; +Net "EB_B3" Loc = "IO_EB_B3"; # Bank_EB1 +Net "EB_B4" Loc = "IO_EB_B4"; # _____________ +Net "EB_B5" Loc = "IO_EB_B5"; # VDD_NA ------- | 1 2 | -------- GND +Net "EB_B6" Loc = "IO_EB_B6"; # EB_A0 ------- | 3 4 | -------- EB_B0 +Net "EB_B7" Loc = "IO_EB_B7"; # EB_A1 ------- | 5 6 | -------- EB_B1 +Net "EB_B8" Loc = "IO_EB_B8"; # EB_A2 ------- | 7 8 | -------- EB_B2 +# --------------------------# # EB_A3 ------- | 9 10 | -------- EB_B2 +# Lower Row # EB_A4 ------- | 11 12 | -------- EB_B2 +# BOTTOM LEFT PIN IS VDD # # EB_A5 ------- | 13 14 | -------- EB_B2 +Net "EB_A0" Loc = "IO_EB_A0"; # EB_A6 ------- | 15 16 | -------- EB_B2 +Net "EB_A1" Loc = "IO_EB_A1"; # EB_A7 ------- | 17 18 | -------- EB_B2 +Net "EB_A2" Loc = "IO_EB_A2"; # EB_a8 ------- | 19 20 | -------- EB_B2 +Net "EB_A3" Loc = "IO_EB_A3"; # _____________ +Net "EB_A4" Loc = "IO_EB_A4"; +Net "EB_A5" Loc = "IO_EB_A5"; +Net "EB_A6" Loc = "IO_EB_A6"; +Net "EB_A7" Loc = "IO_EB_A7"; +Net "EB_A8" Loc = "IO_EB_A8"; + +#======================================================================== +# BANK_MISC1 +#======================================================================== +# BANK_MISC1 is the big one to the right of the board and the configuration + text-picture below is taking into account that you have +# the Olimex board placed so that the BANK_MISC1 is on the right side(VGA Port is on the left side). +#======================================================================== +# Left Row +# TOP LEFT PIN IS 2.5V +#Net "FPGA_SPI_FWD" Loc = "IO_WA_B5" +Net "EA_A8" Loc = "IO_EA_A8"; +Net "EA_B8" Loc = "IO_EA_B8"; +Net "WB_A8" Loc = "IO_WB_A8"; +Net "WB_B8" Loc = "IO_WB_B8"; +Net "SB_B3" Loc = "IO_SB_B3"; +Net "SB_B2" Loc = "IO_SB_B2"; +Net "SB_A2" Loc = "IO_SB_A2"; +Net "SB_B1" Loc = "IO_SB_B1"; +Net "SB_A1" Loc = "IO_SB_A1"; +Net "SB_B0" Loc = "IO_SB_B0"; # MISC1 +Net "SB_A0" Loc = "IO_SB_A0"; # _____________ +Net "FPGA_RESET_IN" Loc = "RST_N"; # 2.5V ----------| 1 2 | -------- 1.8V +# SECOND TO LAST PIN # FPGA_SPI_FWD - | 3 4 | -------- WC_B3 +# IS NET-(BANK_MISC1-PAD31) # # EA_A8 -------- | 5 6 | -------- WC_A3 +# BOTTOM LEFT PIN IS GND # # EA_B8 -------- | 7 8 | -------- WC_B2 +# --------------------------# # WB_A8 -------- | 9 10 | -------- WC_A2 +# Right Row # # WB_B8 -------- | 11 12 | -------- WC_B1 +# TOP RIGHT PIN IN 1.8V # # SB_B3 -------- | 13 14 | -------- WC_A1 +Net "WC_B3" Loc = "IO_WC_B3"; # SB_A3 -------- | 15 16 | -------- WC_B0 +Net "WC_A3" Loc = "IO_WC_A3"; # SB_B2 -------- | 17 18 | -------- WC_A0 +Net "WC_B2" Loc = "IO_WC_B2"; # SB_A2 -------- | 19 20 | -------- SER_CLK_N +Net "WC_A2" Loc = "IO_WC_A2"; # SB_B1 -------- | 21 22 | -------- SER_CLK_P +Net "WC_B1" Loc = "IO_WC_B1"; # SB_A1 -------- | 23 24 | -------- SER_TX_P +Net "WC_A1" Loc = "IO_WC_A1"; # SB_B0 -------- | 25 26 | -------- SER_TX_N +Net "WC_B0" Loc = "IO_WC_B0"; # SB_A0 -------- | 27 28 | -------- SER_RX_N +Net "WC_A0" Loc = "IO_WC_A0"; # FPGA_RESET_IN | 29 30 | -------- SER_TX_P + # CLK0 ----------| 31 32 | -------- CLK3 + # GND ----------| 33 34 | -------- GND +## Serdes # _____________ +# Note!: Take in mind that SerDes is not working when VDD_CORE = 0.9V(Low power mode) because VDDSER and VDDSER_PLL have got minimum working voltage 0.95V! +Net "SER_CLK_N" Loc = "IO_SER_CLK_N"; +Net "SER_CLK_P" Loc = "IO_SER_CLK_P"; +Net "SER_TX_P" Loc = "IO_SER_TX_P"; +Net "SER_TX_N" Loc = "IO_SER_TX_N"; +Net "SER_RX_N" Loc = "IO_SER_RX_N"; +Net "SER_RX_P" Loc = "IO_SER_RX_P"; +# SECOND TO LAST PIN IS NET-(BANK_MISC1-PAD32) # +# BOTTOM RIGHT PIN IS GND # # + +#======================================================================== +# GPIO +#======================================================================== +# Mostly used for RP2040, change the names to better describe function +#======================================================================== + +Net "GPIO0" Loc = "IO_SA_A0"; +Net "GPIO1" Loc = "IO_SA_B0"; +Net "GPIO2" Loc = "IO_SA_A1"; +Net "GPIO3" Loc = "IO_SA_B1"; +Net "GPIO4" Loc = "IO_SA_A2"; +Net "GPIO5" Loc = "IO_SA_B2"; +Net "GPIO6" Loc = "IO_SA_A3"; +Net "GPIO7" Loc = "IO_SA_B3"; +Net "GPIO8" Loc = "IO_SA_A4"; +Net "GPIO9" Loc = "IO_SA_B4"; +Net "GPIO10" Loc = "IO_SA_A5"; +Net "GPIO11" Loc = "IO_SA_B5"; +Net "GPIO14" Loc = "IO_SA_A7"; +Net "GPIO15" Loc = "IO_SA_B7"; +Net "GPIO21" Loc = "IO_SB_B8"; # GPIN1 +Net "GPIO26" Loc = "IO_SB_B4"; +Net "GPIO27" Loc = "IO_SB_A4"; +Net "GPIO28" Loc = "IO_SA_A8"; +Net "GPIO29" Loc = "IO_SA_B8"; + +#======================================================================== +# Generaly used IO Pins +#======================================================================== +# LED, 4 Clocks for PLL +#======================================================================== + +Net "FPGA_LED" Loc = "IO_SB_B6"; # FPGA LED +Net "FPGA_BUT" Loc = "IO_SB_B7"; +Net "CLK0" Loc = "IO_SB_A8"; # CLK0 +Net "CLK3" Loc = "IO_SB_A5"; +Net "GPIO24" Loc = "IO_SB_A6"; # CLK2 +Net "GPIO23" Loc = "IO_SB_A7"; # CLK1 + +#======================================================================== +# UART Interface +#======================================================================== +# There is a mistake on the schematic, these need to be flipped as below +#======================================================================== +Net "DBG_UART_RX" Loc = "IO_SA_A6"; # GPIO12 +Net "DBG_UART_TX" Loc = "IO_SA_B6"; # GPIO13 + +#======================================================================== +# JTAG Interface +#======================================================================== + +Net "JTAG_LED" Loc = "IO_SB_B5"; # GPIO25 +Net "JTAG_TCK" Loc = "IO_WA_A5"; # GPIO18 +Net "JTAG_TMS" Loc = "IO_WA_B4"; # GPIO19 +Net "JTAG_TDI" Loc = "IO_WA_A4"; # GPIO16 +Net "JTAG_TDO" Loc = "IO_WA_B3"; # GPIO17 + +#======================================================================== +# SPI Configuration +#======================================================================== + +Net "FPGA_SPI_CLK" Loc = "IO_WA_B8"; +Net "FPGA_SPI_CSN" Loc = "IO_WA_A8"; +Net "FPGA_SPI_D0" Loc = "IO_WA_B7"; +Net "FPGA_SPI_D1" Loc = "IO_WA_A7"; +Net "FPGA_SPI_D2" Loc = "IO_WA_B6"; +Net "FPGA_SPI_D3" Loc = "IO_WA_A6"; +Net "FPGA_SPI_FWD" Loc = "IO_WA_B5"; + +#======================================================================== +# PS2 Pin Configuration +#======================================================================== + +NET "PS2_CLK" Loc = "IO_WB_A0"; +NET "PS2_DATA" Loc = "IO_WB_B0"; + +#======================================================================== +# VGA Configuration +#======================================================================== +# TODO: Change the values to arrays maybe? +#======================================================================== + +Net "VGA_HSync" Loc = "IO_WB_A1"; +Net "VGA_VSync" Loc = "IO_WB_B1"; +Net "VGA_Red_3" Loc = "IO_WB_A2"; +Net "VGA_Red_2" Loc = "IO_WB_B2"; +Net "VGA_Red_1" Loc = "IO_WB_A3"; +Net "VGA_Red_0" Loc = "IO_WB_B3"; +Net "VGA_Green_3" Loc = "IO_WB_A4"; +Net "VGA_Green_2" Loc = "IO_WB_B4"; +Net "VGA_Green_1" Loc = "IO_WB_A5"; +Net "VGA_Green_0" Loc = "IO_WB_B5"; +Net "VGA_Blue_3" Loc = "IO_WB_A6"; +Net "VGA_Blue_2" Loc = "IO_WB_B6"; +Net "VGA_Blue_1" Loc = "IO_WB_A7"; +Net "VGA_Blue_0" Loc = "IO_WB_B7"; + +#======================================================================== +## PSRAM Configuration +#======================================================================== + +Net "PSRAM_CS" Loc = "IO_WC_A4"; +Net "PSRAM_SCLK" Loc = "IO_WC_B4"; +Net "PSRAM_DATA0" Loc = "IO_WC_A5"; +Net "PSRAM_DATA1" Loc = "IO_WC_B5"; +Net "PSRAM_DATA2" Loc = "IO_WC_A6"; +Net "PSRAM_DATA3" Loc = "IO_WC_B6"; +Net "PSRAM_DATA4" Loc = "IO_WC_A7"; +Net "PSRAM_DATA5" Loc = "IO_WC_B7"; +Net "PSRAM_DATA6" Loc = "IO_WC_A8"; +Net "PSRAM_DATA7" Loc = "IO_WC_B8"; + + +#======================================================================== +# UEXT +#======================================================================== + # _______________ +Net "UEXT_TXD" Loc = "IO_EA_A0"; # 3.3V ----- | 1 -- -- 2 | ----- GND +Net "UEXT_RXD" Loc = "IO_EA_B0"; # UEXT_TXD - | 3 -- -- 4 | -UEXT_RXD +Net "UEXT_SCL" Loc = "IO_EA_A1"; # UEXT_SCL - | 5 -- -- 6 | -UEXT_SDA +Net "UEXT_SDA" Loc = "IO_EA_B1"; # UEXT_MISCO | 7 -- -- 8 | -UEXT_MOSI +Net "UEXT_MISO" Loc = "IO_EA_A2"; # UEXT_SCK - | 9 -- --10 | -UEXT_CS +Net "UEXT_MOSI" Loc = "IO_EA_B2"; # _______________ +Net "UEXT_SCK" Loc = "IO_EA_A3"; +Net "UEXT_CS" Loc = "IO_EA_B3"; + +#======================================================================== +# PMOD +#======================================================================== + # ___________ +Net "PMOD_1" Loc = "IO_EA_A4"; # | 1 7 | +Net "PMOD_7" Loc = "IO_EA_B4"; # | 2 8 | +Net "PMOD_2" Loc = "IO_EA_A5"; # | 3 9 | +Net "PMOD_8" Loc = "IO_EA_B5"; # | 4 10 | +Net "PMOD_3" Loc = "IO_EA_A6"; # GND -| 5 11 | --- GND +Net "PMOD_9" Loc = "IO_EA_B6"; # 3-3V-| 6 12 | --- 3.3V +Net "PMOD_4" Loc = "IO_EA_B7"; # ___________ +Net "PMOD_10" Loc = "IO_EA_A7"; + +#======================================================================== +# End of hardware constraints GateMateA1-EVB.ccf +#========================================================================