slederer/Tridora-CPU
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages 3 Wiki Activity Actions

tridoracpu: cache bug fixes

Browse source
This commit is contained in:
slederer 2025-03-29 01:29:16 +01:00
parent 651a451d53
commit 8abd9fc126
5 changed files with 27 additions and 27 deletions
Download patch file Download diff file Expand all files Collapse all files

2
lib/rommon.s
View file

@ -810,7 +810,7 @@ WAIT1LOOP:
%include "sdcardboot.s" %include "sdcardboot.s"
.CPOOL .CPOOL
MESSAGE: MESSAGE:
.BYTE 13,10,"ROM Monitor v3.0.3", 13, 10, .BYTE 13,10,"ROM Monitor v3.1.0", 13, 10,
"Set A)ddress D)eposit eX)amine L)oad G)o B)oot",13,10,0 "Set A)ddress D)eposit eX)amine L)oad G)o B)oot",13,10,0
PROMPT2: PROMPT2:
.BYTE "]> ",0 .BYTE "]> ",0

38
tridoracpu/tridoracpu.srcs/dram_bridge.v
View file

@ -106,10 +106,9 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
.sys_rst (rst_n) .sys_rst (rst_n)
); );
reg [DRAM_DATA_WIDTH-1:0] ins_cache; (*KEEP*) reg [DRAM_DATA_WIDTH-1:0] ins_cache;
reg [DRAM_ADDR_WIDTH-1:4] cached_addr; (*KEEP*) reg [DRAM_ADDR_WIDTH-1:4] cached_addr;
wire cache_hit = mem_read_ins && (cached_addr == mem_addr[DRAM_ADDR_WIDTH:4]); (*KEEP*) wire cache_hit = mem_read_enable && mem_read_ins && (cached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4]);
wire [DRAM_DATA_WIDTH-1:0] read_data_wrapper = cache_hit ? ins_cache : app_rd_data;
reg [WIDTH-1:0] read_buf; reg [WIDTH-1:0] read_buf;
reg read_inprogress = 0; reg read_inprogress = 0;
@ -123,20 +122,22 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
// select a word from the 128 bits transferred by the dram controller // select a word from the 128 bits transferred by the dram controller
// according to the lower bits of the address (ignoring bits 1:0) // according to the lower bits of the address (ignoring bits 1:0)
wire [WIDTH-1:0] read_word;
wire [1:0] word_sel = mem_addr[3:2]; wire [1:0] word_sel = mem_addr[3:2];
// assign read_word = word_sel == 3'b11 ? app_rd_data[31:0] : wire [WIDTH-1:0] read_word =
// word_sel == 3'b10 ? app_rd_data[63:32] : word_sel == 3'b11 ? app_rd_data[31:0] :
// word_sel == 3'b01 ? app_rd_data[95:64] : word_sel == 3'b10 ? app_rd_data[63:32] :
// app_rd_data[127:96]; word_sel == 3'b01 ? app_rd_data[95:64] :
app_rd_data[127:96];
assign read_word = word_sel == 3'b11 ? read_data_wrapper[31:0] : wire [WIDTH-1:0] read_cached_word =
word_sel == 3'b10 ? read_data_wrapper[63:32] : word_sel == 3'b11 ? ins_cache[31:0] :
word_sel == 3'b01 ? read_data_wrapper[95:64] : word_sel == 3'b10 ? ins_cache[63:32] :
read_data_wrapper[127:96]; word_sel == 3'b01 ? ins_cache[95:64] :
ins_cache[127:96];
assign mem_read_data = app_rd_data_valid ? read_word : read_buf; (*KEEP*) assign mem_read_data = cache_hit ? read_cached_word :
app_rd_data_valid ? read_word : read_buf;
// set the write mask according to the lower bits of the address // set the write mask according to the lower bits of the address
// (ignoring bit 0) // (ignoring bit 0)
@ -161,10 +162,10 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
always @(posedge dram_front_clk) always @(posedge dram_front_clk)
begin begin
if(mem_read_enable && mem_read_ins && ~cache_hit && app_rd_data_valid) if(dram_read_enable && mem_read_ins && app_rd_data_valid)
begin begin
ins_cache <= mem_read_data; ins_cache <= app_rd_data;
cached_addr <= mem_addr[DRAM_ADDR_WIDTH:4]; cached_addr <= mem_addr[DRAM_ADDR_WIDTH-1:4];
end end
end end
@ -176,5 +177,8 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
read_inprogress <= 0; read_inprogress <= 0;
if(dram_read_enable & app_rd_data_valid) if(dram_read_enable & app_rd_data_valid)
read_buf <= mem_read_data; read_buf <= mem_read_data;
else
if (mem_read_enable & cache_hit)
read_buf <= read_cached_word;
end end
endmodule endmodule

2
tridoracpu/tridoracpu.srcs/sdspi.v
View file

@ -107,7 +107,7 @@ module sdspi(
tx_fifo_empty tx_fifo_empty
); );
fifo #(.ADDR_WIDTH(8)) rx_fifo(clk, reset, fifo #(.ADDR_WIDTH(10)) rx_fifo(clk, reset,
rx_fifo_wr_en, rx_fifo_rd_en, rx_fifo_wr_en, rx_fifo_rd_en,
rx_shifter, rx_fifo_out, rx_shifter, rx_fifo_out,
rx_fifo_full, rx_fifo_full,

4
tridoracpu/tridoracpu.srcs/top.v
View file

@ -68,7 +68,7 @@ module top(
localparam ADDR_WIDTH = 32, WIDTH = 32, localparam ADDR_WIDTH = 32, WIDTH = 32,
ROMADDR_WIDTH = 11, IOADDR_WIDTH = 11, IOADDR_SEL = 4; ROMADDR_WIDTH = 11, IOADDR_WIDTH = 11, IOADDR_SEL = 4;
wire [ADDR_WIDTH-1:0] mem_addr; (* KEEP *) wire [ADDR_WIDTH-1:0] mem_addr;
wire [WIDTH-1:0] mem_read_data; wire [WIDTH-1:0] mem_read_data;
wire [WIDTH-1:0] mem_write_data; wire [WIDTH-1:0] mem_write_data;
(* KEEP *) wire mem_wait; (* KEEP *) wire mem_wait;
@ -91,7 +91,7 @@ module top(
wire [ADDR_WIDTH-1:0] dram_addr; wire [ADDR_WIDTH-1:0] dram_addr;
wire [WIDTH-1:0] dram_read_data, dram_write_data; wire [WIDTH-1:0] dram_read_data, dram_write_data;
wire dram_read_enable, dram_write_enable, dram_wait; wire dram_read_enable, dram_write_enable, dram_wait;
wire dram_read_ins; (* KEEP *) wire dram_read_ins;
dram_bridge dram_bridge0 (dram_addr, dram_bridge dram_bridge0 (dram_addr,
dram_read_data, dram_write_data, dram_read_enable, dram_write_enable, dram_read_data, dram_write_data, dram_read_enable, dram_write_enable,

8
tridoracpu/tridoracpu.xpr
View file

@ -361,9 +361,7 @@
</Run> </Run>
<Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" ParallelReportGen="true"> <Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -399,9 +397,7 @@
</Run> </Run>
<Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" ParallelReportGen="true"> <Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"/> <Step Id="opt_design"/>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>