diff --git a/lib/rommon.s b/lib/rommon.s
index 4828008..a1034c5 100644
--- a/lib/rommon.s
+++ b/lib/rommon.s
@@ -810,7 +810,7 @@ WAIT1LOOP:
%include "sdcardboot.s"
.CPOOL
MESSAGE:
- .BYTE 13,10,"ROM Monitor v3.0.3", 13, 10,
+ .BYTE 13,10,"ROM Monitor v3.1.0", 13, 10,
"Set A)ddress D)eposit eX)amine L)oad G)o B)oot",13,10,0
PROMPT2:
.BYTE "]> ",0
diff --git a/tridoracpu/tridoracpu.srcs/dram_bridge.v b/tridoracpu/tridoracpu.srcs/dram_bridge.v
index 1b60fd0..c3f948a 100644
--- a/tridoracpu/tridoracpu.srcs/dram_bridge.v
+++ b/tridoracpu/tridoracpu.srcs/dram_bridge.v
@@ -106,10 +106,9 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
.sys_rst (rst_n)
);
- reg [DRAM_DATA_WIDTH-1:0] ins_cache;
- reg [DRAM_ADDR_WIDTH-1:4] cached_addr;
- wire cache_hit = mem_read_ins && (cached_addr == mem_addr[DRAM_ADDR_WIDTH:4]);
- wire [DRAM_DATA_WIDTH-1:0] read_data_wrapper = cache_hit ? ins_cache : app_rd_data;
+ (*KEEP*) reg [DRAM_DATA_WIDTH-1:0] ins_cache;
+ (*KEEP*) reg [DRAM_ADDR_WIDTH-1:4] cached_addr;
+ (*KEEP*) wire cache_hit = mem_read_enable && mem_read_ins && (cached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4]);
reg [WIDTH-1:0] read_buf;
reg read_inprogress = 0;
@@ -123,20 +122,22 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
// select a word from the 128 bits transferred by the dram controller
// according to the lower bits of the address (ignoring bits 1:0)
- wire [WIDTH-1:0] read_word;
wire [1:0] word_sel = mem_addr[3:2];
-// assign read_word = word_sel == 3'b11 ? app_rd_data[31:0] :
-// word_sel == 3'b10 ? app_rd_data[63:32] :
-// word_sel == 3'b01 ? app_rd_data[95:64] :
-// app_rd_data[127:96];
+ wire [WIDTH-1:0] read_word =
+ word_sel == 3'b11 ? app_rd_data[31:0] :
+ word_sel == 3'b10 ? app_rd_data[63:32] :
+ word_sel == 3'b01 ? app_rd_data[95:64] :
+ app_rd_data[127:96];
- assign read_word = word_sel == 3'b11 ? read_data_wrapper[31:0] :
- word_sel == 3'b10 ? read_data_wrapper[63:32] :
- word_sel == 3'b01 ? read_data_wrapper[95:64] :
- read_data_wrapper[127:96];
+ wire [WIDTH-1:0] read_cached_word =
+ word_sel == 3'b11 ? ins_cache[31:0] :
+ word_sel == 3'b10 ? ins_cache[63:32] :
+ word_sel == 3'b01 ? ins_cache[95:64] :
+ ins_cache[127:96];
- assign mem_read_data = app_rd_data_valid ? read_word : read_buf;
+ (*KEEP*) assign mem_read_data = cache_hit ? read_cached_word :
+ app_rd_data_valid ? read_word : read_buf;
// set the write mask according to the lower bits of the address
// (ignoring bit 0)
@@ -161,10 +162,10 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
always @(posedge dram_front_clk)
begin
- if(mem_read_enable && mem_read_ins && ~cache_hit && app_rd_data_valid)
+ if(dram_read_enable && mem_read_ins && app_rd_data_valid)
begin
- ins_cache <= mem_read_data;
- cached_addr <= mem_addr[DRAM_ADDR_WIDTH:4];
+ ins_cache <= app_rd_data;
+ cached_addr <= mem_addr[DRAM_ADDR_WIDTH-1:4];
end
end
@@ -176,5 +177,8 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
read_inprogress <= 0;
if(dram_read_enable & app_rd_data_valid)
read_buf <= mem_read_data;
+ else
+ if (mem_read_enable & cache_hit)
+ read_buf <= read_cached_word;
end
endmodule
diff --git a/tridoracpu/tridoracpu.srcs/sdspi.v b/tridoracpu/tridoracpu.srcs/sdspi.v
index 7141288..9f5c84d 100644
--- a/tridoracpu/tridoracpu.srcs/sdspi.v
+++ b/tridoracpu/tridoracpu.srcs/sdspi.v
@@ -107,7 +107,7 @@ module sdspi(
tx_fifo_empty
);
- fifo #(.ADDR_WIDTH(8)) rx_fifo(clk, reset,
+ fifo #(.ADDR_WIDTH(10)) rx_fifo(clk, reset,
rx_fifo_wr_en, rx_fifo_rd_en,
rx_shifter, rx_fifo_out,
rx_fifo_full,
diff --git a/tridoracpu/tridoracpu.srcs/top.v b/tridoracpu/tridoracpu.srcs/top.v
index 0496573..00066fe 100644
--- a/tridoracpu/tridoracpu.srcs/top.v
+++ b/tridoracpu/tridoracpu.srcs/top.v
@@ -68,7 +68,7 @@ module top(
localparam ADDR_WIDTH = 32, WIDTH = 32,
ROMADDR_WIDTH = 11, IOADDR_WIDTH = 11, IOADDR_SEL = 4;
- wire [ADDR_WIDTH-1:0] mem_addr;
+ (* KEEP *) wire [ADDR_WIDTH-1:0] mem_addr;
wire [WIDTH-1:0] mem_read_data;
wire [WIDTH-1:0] mem_write_data;
(* KEEP *) wire mem_wait;
@@ -91,7 +91,7 @@ module top(
wire [ADDR_WIDTH-1:0] dram_addr;
wire [WIDTH-1:0] dram_read_data, dram_write_data;
wire dram_read_enable, dram_write_enable, dram_wait;
- wire dram_read_ins;
+ (* KEEP *) wire dram_read_ins;
dram_bridge dram_bridge0 (dram_addr,
dram_read_data, dram_write_data, dram_read_enable, dram_write_enable,
diff --git a/tridoracpu/tridoracpu.xpr b/tridoracpu/tridoracpu.xpr
index 017971d..05c7b30 100644
--- a/tridoracpu/tridoracpu.xpr
+++ b/tridoracpu/tridoracpu.xpr
@@ -361,9 +361,7 @@
-
- Vivado Synthesis Defaults
-
+
@@ -399,9 +397,7 @@
-
- Default settings for Implementation.
-
+