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tridoracpu: cache bug fixes

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slederer 2025-03-29 01:29:16 +01:00
parent 651a451d53
commit 8abd9fc126
5 changed files with 27 additions and 27 deletions
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4
tridoracpu/tridoracpu.srcs/top.v
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@ -68,7 +68,7 @@ module top(
localparam ADDR_WIDTH = 32, WIDTH = 32,
ROMADDR_WIDTH = 11, IOADDR_WIDTH = 11, IOADDR_SEL = 4;
wire [ADDR_WIDTH-1:0] mem_addr;
(* KEEP *) wire [ADDR_WIDTH-1:0] mem_addr;
wire [WIDTH-1:0] mem_read_data;
wire [WIDTH-1:0] mem_write_data;
(* KEEP *) wire mem_wait;
@ -91,7 +91,7 @@ module top(
wire [ADDR_WIDTH-1:0] dram_addr;
wire [WIDTH-1:0] dram_read_data, dram_write_data;
wire dram_read_enable, dram_write_enable, dram_wait;
wire dram_read_ins;
(* KEEP *) wire dram_read_ins;
dram_bridge dram_bridge0 (dram_addr,
dram_read_data, dram_write_data, dram_read_enable, dram_write_enable,