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tridoracpu: cache bug fixes

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slederer 2025-03-29 01:29:16 +01:00
parent 651a451d53
commit 8abd9fc126
5 changed files with 27 additions and 27 deletions
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38
tridoracpu/tridoracpu.srcs/dram_bridge.v
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@ -106,10 +106,9 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
.sys_rst (rst_n)
);
reg [DRAM_DATA_WIDTH-1:0] ins_cache;
reg [DRAM_ADDR_WIDTH-1:4] cached_addr;
wire cache_hit = mem_read_ins && (cached_addr == mem_addr[DRAM_ADDR_WIDTH:4]);
wire [DRAM_DATA_WIDTH-1:0] read_data_wrapper = cache_hit ? ins_cache : app_rd_data;
(*KEEP*) reg [DRAM_DATA_WIDTH-1:0] ins_cache;
(*KEEP*) reg [DRAM_ADDR_WIDTH-1:4] cached_addr;
(*KEEP*) wire cache_hit = mem_read_enable && mem_read_ins && (cached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4]);
reg [WIDTH-1:0] read_buf;
reg read_inprogress = 0;
@ -123,20 +122,22 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
// select a word from the 128 bits transferred by the dram controller
// according to the lower bits of the address (ignoring bits 1:0)
wire [WIDTH-1:0] read_word;
wire [1:0] word_sel = mem_addr[3:2];
// assign read_word = word_sel == 3'b11 ? app_rd_data[31:0] :
// word_sel == 3'b10 ? app_rd_data[63:32] :
// word_sel == 3'b01 ? app_rd_data[95:64] :
// app_rd_data[127:96];
wire [WIDTH-1:0] read_word =
word_sel == 3'b11 ? app_rd_data[31:0] :
word_sel == 3'b10 ? app_rd_data[63:32] :
word_sel == 3'b01 ? app_rd_data[95:64] :
app_rd_data[127:96];
assign read_word = word_sel == 3'b11 ? read_data_wrapper[31:0] :
word_sel == 3'b10 ? read_data_wrapper[63:32] :
word_sel == 3'b01 ? read_data_wrapper[95:64] :
read_data_wrapper[127:96];
wire [WIDTH-1:0] read_cached_word =
word_sel == 3'b11 ? ins_cache[31:0] :
word_sel == 3'b10 ? ins_cache[63:32] :
word_sel == 3'b01 ? ins_cache[95:64] :
ins_cache[127:96];
assign mem_read_data = app_rd_data_valid ? read_word : read_buf;
(*KEEP*) assign mem_read_data = cache_hit ? read_cached_word :
app_rd_data_valid ? read_word : read_buf;
// set the write mask according to the lower bits of the address
// (ignoring bit 0)
@ -161,10 +162,10 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
always @(posedge dram_front_clk)
begin
if(mem_read_enable && mem_read_ins && ~cache_hit && app_rd_data_valid)
if(dram_read_enable && mem_read_ins && app_rd_data_valid)
begin
ins_cache <= mem_read_data;
cached_addr <= mem_addr[DRAM_ADDR_WIDTH:4];
ins_cache <= app_rd_data;
cached_addr <= mem_addr[DRAM_ADDR_WIDTH-1:4];
end
end
@ -176,5 +177,8 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
read_inprogress <= 0;
if(dram_read_enable & app_rd_data_valid)
read_buf <= mem_read_data;
else
if (mem_read_enable & cache_hit)
read_buf <= read_cached_word;
end
endmodule