slederer/Tridora-CPU
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages 3 Wiki Activity Actions

tdraudio: add direct amplitude control

Browse source
This commit is contained in:
slederer 2025-09-29 19:10:48 +02:00
parent 57430a4df6
commit 12033bb6d2
2 changed files with 30 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

29
tridoracpu/tridoracpu.srcs/tdraudio.v
View file

@ -42,17 +42,22 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
reg [LFSR_WIDTH-1:0] lfsr;
wire [AMP_WIDTH-1:0] noise_out;
reg direct_amp_enable;
//assign rd_data = {{DATA_WIDTH-8-CLOCK_DIV_WIDTH{1'b0}}, div_count, {7{1'b0}}, channel_enable};
assign rd_data = {8'b0, amp_start, {6{1'b0}}, noise_enable, channel_enable};
assign rd_data = {8'b0, amp_start,
{4{1'b0}}, amp_phase, direct_amp_enable, noise_enable, channel_enable};
assign amp_val = amp_out;
assign running = channel_enable;
wire ctl_reg_write = wr_en && (reg_sel == TDRAU_REG_CTL);
/* channel enable flag */
always @(posedge clk)
begin
if(reset)
channel_enable <= 0;
else if (wr_en && (reg_sel == TDRAU_REG_CTL))
else if (ctl_reg_write)
channel_enable <= wr_data[0];
end
@ -97,7 +102,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
begin
if(reset)
noise_enable <= 0;
else if (wr_en && (reg_sel == TDRAU_REG_CTL))
else if (ctl_reg_write)
noise_enable <= wr_data[1];
end
@ -107,7 +112,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
if (reset)
lfsr <= LFSR_INIT;
else
if (wr_en && (reg_sel == TDRAU_REG_CTL) && wr_data[1])
if (ctl_reg_write && wr_data[1])
lfsr <= LFSR_INIT;
else
if (channel_enable && noise_enable)
@ -119,6 +124,15 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
assign noise_out = lfsr[0] ? amp_start : ~amp_start;
/* direct amplitude enable flag */
always @(posedge clk)
begin
if(reset)
direct_amp_enable <= 0;
else if (ctl_reg_write)
direct_amp_enable <= wr_data[2];
end
/* amplitude out */
always @(posedge clk)
begin
@ -132,8 +146,9 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
begin
if (div_count == 0) // invert amplitude on clock tick
begin
amp_out <= noise_enable ? noise_out :
amp_phase ? amp_start : ~amp_start;
amp_out <= direct_amp_enable ? amp_start :
noise_enable ? noise_out :
amp_phase ? amp_start : ~amp_start;
amp_phase <= ~amp_phase;
end
end
@ -141,7 +156,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
amp_out <= 0;
// reset phase bit when enabling the channel
if (wr_en && (reg_sel == TDRAU_REG_CTL) && wr_data[0])
if (ctl_reg_write && wr_data[0])
// when channel is enabled, phase will be flipped on next tick
// because div_count will become zero
amp_phase <= 1;