diff --git a/tridoracpu/tridoracpu.srcs/tdraudio.v b/tridoracpu/tridoracpu.srcs/tdraudio.v
index 5c19264..9cb1d74 100644
--- a/tridoracpu/tridoracpu.srcs/tdraudio.v
+++ b/tridoracpu/tridoracpu.srcs/tdraudio.v
@@ -42,17 +42,22 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
     reg [LFSR_WIDTH-1:0] lfsr;
     wire [AMP_WIDTH-1:0] noise_out;
 
+    reg direct_amp_enable;
+
     //assign rd_data = {{DATA_WIDTH-8-CLOCK_DIV_WIDTH{1'b0}}, div_count, {7{1'b0}}, channel_enable};
-    assign rd_data = {8'b0, amp_start, {6{1'b0}}, noise_enable, channel_enable};
+    assign rd_data = {8'b0, amp_start,
+        {4{1'b0}}, amp_phase, direct_amp_enable, noise_enable, channel_enable};
     assign amp_val = amp_out;
     assign running = channel_enable;
 
+    wire ctl_reg_write = wr_en && (reg_sel == TDRAU_REG_CTL);
+
     /* channel enable flag */
     always @(posedge clk)
     begin
         if(reset)
             channel_enable <= 0;
-        else if (wr_en && (reg_sel == TDRAU_REG_CTL))
+        else if (ctl_reg_write)
             channel_enable <= wr_data[0];
     end
 
@@ -97,7 +102,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
     begin
         if(reset)
             noise_enable <= 0;
-        else if (wr_en && (reg_sel == TDRAU_REG_CTL))
+        else if (ctl_reg_write)
             noise_enable <= wr_data[1];
     end
 
@@ -107,7 +112,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
         if (reset)
             lfsr <= LFSR_INIT;
         else
-        if (wr_en && (reg_sel == TDRAU_REG_CTL) && wr_data[1])
+        if (ctl_reg_write && wr_data[1])
             lfsr <= LFSR_INIT;
         else
         if (channel_enable && noise_enable)
@@ -119,6 +124,15 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
 
     assign noise_out = lfsr[0] ? amp_start : ~amp_start;
 
+    /* direct amplitude enable flag */
+    always @(posedge clk)
+    begin
+        if(reset)
+            direct_amp_enable <= 0;
+        else if (ctl_reg_write)
+            direct_amp_enable <= wr_data[2];
+    end
+
     /* amplitude out */
     always @(posedge clk)
     begin
@@ -132,8 +146,9 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
         begin
             if (div_count == 0) // invert amplitude on clock tick
             begin
-                amp_out <= noise_enable ? noise_out :
-                        amp_phase ? amp_start : ~amp_start;
+                amp_out <= direct_amp_enable ?  amp_start :
+                            noise_enable ?      noise_out :
+                            amp_phase ?         amp_start : ~amp_start;
                 amp_phase <= ~amp_phase;
             end
         end
@@ -141,7 +156,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
             amp_out <= 0;
 
         // reset phase bit when enabling the channel
-        if (wr_en && (reg_sel == TDRAU_REG_CTL) && wr_data[0])
+        if (ctl_reg_write && wr_data[0])
             // when channel is enabled, phase will be flipped on next tick
             // because div_count will become zero
             amp_phase <= 1;
diff --git a/tridoracpu/tridoracpu.xpr b/tridoracpu/tridoracpu.xpr
index ba7a2ef..4bbcb9d 100644
--- a/tridoracpu/tridoracpu.xpr
+++ b/tridoracpu/tridoracpu.xpr
@@ -356,12 +356,14 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="22">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, lowering multiplier threshold of inference into DSP blocks, moving  shift register into BRAM, applying lower thresholds for use of carry chain in comparators and also area optimized mux optimizations" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, applying lower thresholds for use of carry chain in comparators and also area optimized mux optimizations." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Flow_AreaOptimized_medium" Flow="Vivado Synthesis 2024"/>
+        <StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2024">
+          <Desc>Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, applying lower thresholds for use of carry chain in comparators and also area optimized mux optimizations.</Desc>
+        </StratHandle>
         <Step Id="synth_design">
           <Option Id="ControlSetOptThreshold">1</Option>
-          <Option Id="Directive">2</Option>
+          <Option Id="Directive">1</Option>
         </Step>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -381,7 +383,9 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>