272 lines
7.7 KiB
Verilog
272 lines
7.7 KiB
Verilog
`timescale 1ns / 1ps
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// waveform generator module (pulse wave or noise)
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module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22,
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AMP_WIDTH=16, AMP_BIAS=32768) (
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input wire clk,
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input wire reset,
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input wire [1:0] reg_sel,
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output wire [DATA_WIDTH-1:0] rd_data,
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input wire [DATA_WIDTH-1:0] wr_data,
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input wire rd_en,
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input wire wr_en,
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output wire [AMP_WIDTH-1:0] amp_val,
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output wire running
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);
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localparam TDRAU_REG_CTL = 0; /* control register */
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localparam TDRAU_REG_CLK = 1; /* clock divider register */
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localparam TDRAU_REG_AMP = 2; /* amplitude (volume) register */
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// localparam LFSR_WIDTH = 18;
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// localparam LFSR_TAP_IDX_1 = 17;
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// localparam LFSR_TAP_IDX_2 = 10;
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// localparam LFSR_INIT = 'h3CBE6;
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localparam LFSR_WIDTH = 23;
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localparam LFSR_INIT = 'h1;
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reg channel_enable;
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reg [CLOCK_DIV_WIDTH-1:0] clock_div;
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reg [CLOCK_DIV_WIDTH-1:0] div_count;
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reg amp_phase;
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reg [AMP_WIDTH-1:0] amp_start;
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reg [AMP_WIDTH-1:0] amp_out;
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reg noise_enable;
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reg [LFSR_WIDTH-1:0] lfsr;
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wire [AMP_WIDTH-1:0] noise_out;
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reg direct_amp_enable;
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//assign rd_data = {{DATA_WIDTH-8-CLOCK_DIV_WIDTH{1'b0}}, div_count, {7{1'b0}}, channel_enable};
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assign rd_data = {8'b0, amp_start,
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{6{1'b0}}, amp_phase, channel_enable};
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assign amp_val = amp_out;
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assign running = channel_enable;
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wire ctl_reg_write = wr_en && (reg_sel == TDRAU_REG_CTL);
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/* channel enable flag */
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always @(posedge clk)
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begin
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if(reset)
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channel_enable <= 0;
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else if (ctl_reg_write)
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channel_enable <= wr_data[0];
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end
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/* clock divider register */
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always @(posedge clk)
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begin
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if(reset)
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clock_div <= 0;
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else
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if (wr_en && (reg_sel == TDRAU_REG_CLK))
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clock_div <= wr_data;
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end
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/* amplitude register */
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always @(posedge clk)
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begin
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if(reset)
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amp_start <= 0;
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else
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if (wr_en && (reg_sel == TDRAU_REG_AMP))
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amp_start <= wr_data;
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end
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/* divider counter */
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always @(posedge clk)
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begin
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if(channel_enable)
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begin
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if(div_count == 0) // reset counter if it reaches zero
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div_count <= clock_div;
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else
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div_count <= div_count - 1; // else just decrement it
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end
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else
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if (wr_en && (reg_sel == TDRAU_REG_CLK)) // when setting divider,
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div_count <= 1; // start cycle on next clock tick
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end
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/* noise enable flag */
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always @(posedge clk)
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begin
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if(reset)
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noise_enable <= 0;
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else if (ctl_reg_write)
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noise_enable <= wr_data[1];
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end
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/* noise generator (Linear Feedback Shift Register) */
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always @(posedge clk)
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begin
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if (reset)
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lfsr <= LFSR_INIT;
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else
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if (ctl_reg_write && wr_data[1])
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lfsr <= LFSR_INIT;
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else
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if (channel_enable && noise_enable)
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if (div_count == 0)
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//lfsr <= { lfsr[LFSR_TAP_IDX_1] ^ lfsr[LFSR_TAP_IDX_2], lfsr[LFSR_WIDTH-1:1] };
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// shift width and tap bits taken from https://github.com/jotego/jtopl
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lfsr <= { lfsr[LFSR_WIDTH-2:0], lfsr[22] ^ lfsr[9] ^ lfsr[8] ^ lfsr[0]};
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end
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assign noise_out = lfsr[0] ? amp_start : ~amp_start;
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/* direct amplitude enable flag */
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always @(posedge clk)
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begin
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if(reset)
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direct_amp_enable <= 0;
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else if (ctl_reg_write)
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direct_amp_enable <= wr_data[2];
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end
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/* amplitude out */
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always @(posedge clk)
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begin
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if (reset)
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begin
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amp_out <= AMP_BIAS;
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amp_phase <= 1;
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end
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else
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if (channel_enable)
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begin
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if (div_count == 0) // invert amplitude on clock tick
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begin
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amp_out <= direct_amp_enable ? amp_start :
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noise_enable ? noise_out :
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amp_phase ? amp_start : ~amp_start;
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amp_phase <= ~amp_phase;
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end
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end
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else
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amp_out <= AMP_BIAS;
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// reset phase bit when enabling the channel
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if (ctl_reg_write && wr_data[0])
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// when channel is enabled, phase will be flipped on next tick
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// because div_count will become zero
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amp_phase <= 1;
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end
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endmodule
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module tdraudio #(DATA_WIDTH=32) (
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input wire clk,
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input wire reset,
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input wire [6:0] io_addr,
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output wire [DATA_WIDTH-1:0] rd_data,
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input wire [DATA_WIDTH-1:0] wr_data,
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input wire rd_en,
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input wire wr_en,
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output wire pdm_out,
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output wire gain_sel,
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output wire shutdown_n
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);
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localparam CLOCK_DIV_WIDTH = 22;
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localparam AMP_WIDTH = 16;
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localparam DAC_WIDTH = 18;
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wire [4:0] chan_sel = io_addr[6:2];
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wire [1:0] reg_sel = io_addr[1:0];
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wire [AMP_WIDTH-1:0] chan0_amp;
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wire [DATA_WIDTH-1:0] chan0_rd_data;
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wire chan0_running;
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wire chan0_sel = chan_sel == 5'd0;
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wire chan0_rd_en = chan0_sel && rd_en;
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wire chan0_wr_en = chan0_sel && wr_en;
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wire [AMP_WIDTH-1:0] chan1_amp;
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wire [DATA_WIDTH-1:0] chan1_rd_data;
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wire chan1_running;
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wire chan1_sel = chan_sel == 5'd1;
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wire chan1_rd_en = chan1_sel && rd_en;
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wire chan1_wr_en = chan1_sel && wr_en;
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wire [AMP_WIDTH-1:0] chan2_amp;
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wire [DATA_WIDTH-1:0] chan2_rd_data;
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wire chan2_running;
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wire chan2_sel = chan_sel == 5'd2;
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wire chan2_rd_en = chan2_sel && rd_en;
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wire chan2_wr_en = chan2_sel && wr_en;
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wire [AMP_WIDTH-1:0] chan3_amp;
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wire [DATA_WIDTH-1:0] chan3_rd_data;
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wire chan3_running;
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wire chan3_sel = chan_sel == 5'd3;
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wire chan3_rd_en = chan3_sel && rd_en;
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wire chan3_wr_en = chan3_sel && wr_en;
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wire running = chan0_running || chan1_running || chan2_running || chan3_running;
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reg was_running;
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assign rd_data = chan0_sel ? chan0_rd_data :
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chan1_sel ? chan1_rd_data :
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chan2_sel ? chan2_rd_data :
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chan3_sel ? chan3_rd_data :
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{DATA_WIDTH{1'b1}};
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wavegen chan0(clk, reset, reg_sel,
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chan0_rd_data, wr_data,
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chan0_rd_en, chan0_wr_en,
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chan0_amp, chan0_running);
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wavegen chan1(clk, reset, reg_sel,
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chan1_rd_data, wr_data,
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chan1_rd_en, chan1_wr_en,
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chan1_amp, chan1_running);
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wavegen chan2(clk, reset, reg_sel,
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chan2_rd_data, wr_data,
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chan2_rd_en, chan2_wr_en,
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chan2_amp, chan2_running);
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wavegen chan3(clk, reset, reg_sel,
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chan3_rd_data, wr_data,
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chan3_rd_en, chan3_wr_en,
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chan3_amp, chan3_running);
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reg [DAC_WIDTH:0] deltasigma_acc; // one extra bit
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wire [DAC_WIDTH:0] amp_sum = chan0_amp + chan1_amp + chan2_amp + chan3_amp; // also one overflow bit here
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//wire [AMP_WIDTH-1:0] amp_sum_scaled = amp_sum[DAC_WIDTH-2:2]; // shifted right to scale down
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assign gain_sel = 1; // gain select: 0 -> 12dB, 1 -> 6dB
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assign shutdown_n = running;
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/* detect shutdown */
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always @(posedge clk)
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begin
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if (reset)
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was_running <= 0;
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else
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was_running <= running;
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end
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/* delta-sigma DAC */
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always @(posedge clk)
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begin
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if(reset)
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deltasigma_acc <= 0;
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else
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if (running)
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deltasigma_acc <= deltasigma_acc[DAC_WIDTH-1:0] + amp_sum;
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else
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if (!running && was_running) // clear accumulator on shutdown
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deltasigma_acc <= 0;
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end
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/* 1-bit audio output */
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assign pdm_out = deltasigma_acc[DAC_WIDTH];
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endmodule
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