Tridora-CPU/rtl/arty-a7
2024-09-19 00:44:08 +02:00
..
mig_dram_0 import Vivado project 2024-09-19 00:44:08 +02:00
Arty-A7-35-Master.xdc import Vivado project 2024-09-19 00:44:08 +02:00
Arty_C_mig.ucf import Vivado project 2024-09-19 00:44:08 +02:00
sdspi_testbench_behav.wcfg import Vivado project 2024-09-19 00:44:08 +02:00
testbench_behav1.wcfg import Vivado project 2024-09-19 00:44:08 +02:00
tridoracpu.tcl import Vivado project 2024-09-19 00:44:08 +02:00