116 lines
2.2 KiB
Verilog
116 lines
2.2 KiB
Verilog
`timescale 1ns / 1ns
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`default_nettype none
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module fifo_testbench();
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// Test signals
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reg clk = 0;
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reg reset = 0;
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reg wr_en = 0;
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reg rd_en = 0;
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reg [7:0] wr_data = 0;
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wire [7:0] rd_data;
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wire wr_full;
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wire rd_empty;
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parameter CLOCK_NS = 10;
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// Unit Under Test
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fifo #(
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.DATA_WIDTH(8),
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.ADDR_WIDTH(4)
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) UUT (
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.clk(clk),
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.reset(reset),
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.wr_en(wr_en),
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.rd_en(rd_en),
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.rd_data(rd_data),
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.wr_data(wr_data),
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.wr_full(wr_full),
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.rd_empty(rd_empty)
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);
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// testbench clock
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always
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#(CLOCK_NS/2) clk <= ~clk;
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initial
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begin
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// issue reset
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reset = 1'b1;
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#10
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reset = 1'b0;
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#10
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// Write two bytes
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wr_data <= 8'hAB;
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wr_en <= 1'b1;
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#10;
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wr_data <= 8'hCD;
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wr_en <= 1'b1;
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#10;
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wr_en <= 1'b0;
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#10
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// read fifo tail
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if (rd_data == 8'hAB)
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$display("Pass - Byte 1");
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else
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$display("Failed - Byte 2");
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// read/remove byte from tail
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rd_en <= 1'b1;
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#10
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// check next byte
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if (rd_data == 8'hCD)
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$display("Pass - Byte 2");
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else
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$display("Failed - Byte 2");
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// remove 2nd byte
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rd_en <= 1'b1;
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#10
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rd_en <= 1'b0;
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#10
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// Write until full
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rd_en <= 1'b0;
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wr_en <= 1'b0;
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for (integer i = 0; i < 16; i = i + 1) begin
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wr_data <= i;
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wr_en <= 1'b1;
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#10;
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end
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wr_en <= 1'b0;
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if (wr_full)
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$display("Pass - Fifo full");
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else
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$display("Failed - Fifo full");
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// read until empty
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rd_en <= 1'b0;
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wr_en <= 1'b0;
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for (integer i = 0; i < 16; i = i + 1) begin
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rd_en <= 1'b1;
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#10;
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end
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rd_en <= 1'b0;
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if (rd_empty)
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$display("Pass - Fifo empty");
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else
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$display("Failed - Fifo empty");
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$finish();
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end
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initial
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begin
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// Required to dump signals
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$dumpfile("fifo_tb_dump.vcd");
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$dumpvars(0);
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end
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endmodule
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