117 lines
No EOL
3.1 KiB
Verilog
117 lines
No EOL
3.1 KiB
Verilog
`timescale 1ns / 1ps
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module tdraudio #(DATA_WIDTH=32) (
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input wire clk,
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input wire reset,
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input wire [3:0] reg_sel,
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output wire [DATA_WIDTH-1:0] rd_data,
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input wire [DATA_WIDTH-1:0] wr_data,
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input wire rd_en,
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input wire wr_en,
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output wire pdm_out,
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output wire gain_sel,
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output wire shutdown_n
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);
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localparam CLOCK_DIV_WIDTH = 22;
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localparam AMP_WIDTH = 16;
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localparam TDRAU_REG_CTL = 0; /* control register */
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localparam TDRAU_REG_CLK = 1; /* clock divider register */
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localparam TDRAU_REG_AMP = 2; /* amplitude (volume) register */
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wire audio_out;
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reg channel_enable;
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reg [CLOCK_DIV_WIDTH-1:0] clock_div;
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reg [CLOCK_DIV_WIDTH-1:0] div_count;
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reg amp_phase;
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reg [AMP_WIDTH-1:0] amp_start;
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reg [AMP_WIDTH-1:0] amp_out;
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reg [AMP_WIDTH:0] deltasigma_acc;
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assign pdm_out = audio_out;
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assign rd_data = {{DATA_WIDTH-8-CLOCK_DIV_WIDTH{1'b0}}, div_count, {7{1'b0}}, channel_enable};
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assign gain_sel = 1; // gain select: 0 -> 12dB, 1 -> 6dB
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assign shutdown_n = channel_enable;
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/* channel enable flag */
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always @(posedge clk)
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begin
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if(reset)
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channel_enable <= 0;
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else if (wr_en && (reg_sel == TDRAU_REG_CTL))
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channel_enable <= wr_data[0];
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end
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/* clock divider register */
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always @(posedge clk)
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begin
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if(reset)
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clock_div <= 0;
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else
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if (wr_en && (reg_sel == TDRAU_REG_CLK))
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clock_div <= wr_data;
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end
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/* amplitude register */
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always @(posedge clk)
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begin
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if(reset)
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amp_start <= 0;
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else
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if (wr_en && (reg_sel == TDRAU_REG_AMP))
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amp_start <= wr_data;
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end
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/* divider counter */
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always @(posedge clk)
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begin
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if(channel_enable)
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begin
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if(div_count == 0) // reset counter if it reaches zero
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div_count <= clock_div;
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else
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div_count <= div_count - 1; // else just decrement it
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end
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else
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if (wr_en && (reg_sel == TDRAU_REG_CLK))
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div_count <= 1; // start cycle in next clock tick
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end
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/* amplitude out */
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always @(posedge clk)
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begin
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if (reset)
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begin
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amp_out <= 0;
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amp_phase <= 1;
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end
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else
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if (channel_enable && (div_count == 0)) // invert amplitude on clock tick
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begin
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amp_out <= amp_phase ? amp_start : ~amp_start;
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amp_phase <= ~amp_phase;
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end
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// reset phase bit when enabling the channel
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if (wr_en && (reg_sel == TDRAU_REG_CTL) && wr_data[0])
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// when channel is enabled, phase will be flipped on next tick
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// because div_count will become zero
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amp_phase <= 1;
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end
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/* delta-sigma DAC */
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always @(posedge clk)
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begin
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if(reset)
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deltasigma_acc <= 0;
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else
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if (channel_enable)
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deltasigma_acc <= deltasigma_acc[AMP_WIDTH-1:0] + amp_out;
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end
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/* 1-bit audio output */
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assign audio_out = deltasigma_acc[AMP_WIDTH];
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endmodule |