a671a66276
examples: removed 5cubes due to unclear licensing add stuff to gitignore, licenses, README import Vivado project
42 lines
955 B
Verilog
42 lines
955 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 17.01.2021 20:59:29
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// Design Name:
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// Module Name: stack
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module stack
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#(parameter ADDR_WIDTH=4, DATA_WIDTH=16)
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(
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input wire clk,
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input wire [ADDR_WIDTH-1:0] rd_addr,
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input wire [ADDR_WIDTH-1:0] wr_addr,
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input wire wr_enable,
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output wire [DATA_WIDTH-1:0] rd_data,
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input wire [DATA_WIDTH-1:0] wr_data
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);
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reg [DATA_WIDTH-1:0] stack[0:2**ADDR_WIDTH-1];
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always @(posedge clk)
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begin
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if(wr_enable) stack[wr_addr] <= wr_data;
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end
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assign rd_data = stack[rd_addr];
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endmodule
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