slederer a441e7e042 import Vivado project, rearrange Verilog sources		2024-09-27 22:14:57 +02:00
..
mig_a.prj	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
mig_b.prj	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00