28 lines
857 B
Verilog
28 lines
857 B
Verilog
`timescale 1ns / 1ps
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// taken from https://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
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// modified for one read/write-port and one read-only-port,
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/// A parameterized, inferable, true dual-port, dual-clock block RAM in Verilog.
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module palette #(
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parameter SLOTS_WIDTH = 4, COLOR_WIDTH = 12
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) (
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input wire wr_clk,
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input wire rd_clk,
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input wire wr_en,
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input wire [SLOTS_WIDTH-1:0] wr_slot,
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input wire [COLOR_WIDTH-1:0] wr_data,
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input wire [SLOTS_WIDTH-1:0] rd_slot,
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output wire [COLOR_WIDTH-1:0] rd_data
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);
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// Shared memory
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reg [COLOR_WIDTH-1:0] colors [(2**SLOTS_WIDTH)-1:0];
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assign rd_data = colors[rd_slot];
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always @(posedge wr_clk) begin
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if(wr_en) colors[wr_slot] <= wr_data;
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end
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endmodule
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