84 lines
No EOL
2.6 KiB
Verilog
84 lines
No EOL
2.6 KiB
Verilog
`timescale 1ns / 1ps
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// a simple fifo
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module fifo #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 4)(
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input wire clk,
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input wire reset,
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input wire wr_en,
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input wire rd_en,
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input wire [DATA_WIDTH-1:0] wr_data,
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output wire [DATA_WIDTH-1:0] rd_data,
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output wire wr_full,
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output wire rd_empty
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);
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reg [DATA_WIDTH-1:0] mem [0:ADDR_WIDTH-1];
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reg [ADDR_WIDTH:0] head_x = 0; // head and tail have one extra bit
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reg [ADDR_WIDTH:0] tail_x = 0; // for detecting overflows
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wire [ADDR_WIDTH-1:0] head = head_x[ADDR_WIDTH-1:0];
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wire [ADDR_WIDTH-1:0] tail = tail_x[ADDR_WIDTH-1:0];
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assign rd_data = mem[tail];
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// the fifo is full when head and tail pointer are the same
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// and the extra bits differ (a wraparound occured)
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assign wr_full = (head == tail) && (head_x[ADDR_WIDTH] != tail_x[ADDR_WIDTH]);
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// the fifo is empty when head and tail pointer are the same
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// and the extra bits are the same (no wraparound)
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assign rd_empty = (head == tail) && (head_x[ADDR_WIDTH] == tail_x[ADDR_WIDTH]);
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// Writing to FIFO
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always @(posedge clk) begin
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if (wr_en)
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begin
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mem[head[ADDR_WIDTH-1:0]] <= wr_data;
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// move head, possible wraparound
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head_x <= head_x + 1'b1;
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end
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end
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// Reading from FIFO
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always @(posedge clk)
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begin
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if (rd_en)
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begin
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// rd_data always has current tail data
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// move tail, possible wraparound
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tail <= tail + 1'b1;
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end
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end
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// Calculating full/empty flags, referenced from zipcpu.com
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wire [c_DEPTH:0] dblnext, nxtread;
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assign dblnext = wraddr + 2;
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assign nxtread = rdaddr + 1'b1;
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always @(posedge i_Clock, negedge i_Reset)
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// Reset case
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if (!i_Reset)
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begin
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// Reset output flags
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fifo_full <= 1'b0;
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fifo_empty <= 1'b1;
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end else casez({ i_Write_En, i_Read_En, !fifo_full, !fifo_empty })
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4'b01?1: begin // A successful read
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fifo_full <= 1'b0;
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fifo_empty <= (nxtread == wraddr);
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end
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4'b101?: begin // A successful write
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fifo_full <= (dblnext == rdaddr);
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fifo_empty <= 1'b0;
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end
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4'b11?0: begin // Successful write, failed read
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fifo_full <= 1'b0;
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fifo_empty <= 1'b0;
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end
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4'b11?1: begin // Successful read and write
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fifo_full <= fifo_full;
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fifo_empty <= 1'b0;
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end
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default: begin end
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endcase
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endmodule |