slederer 937369f60b lib,examples: changes for new register address mapping		2026-01-28 01:15:16 +01:00
..
tridoracpu.srcs	lib,examples: changes for new register address mapping	2026-01-28 01:15:16 +01:00
sdspi_testbench_behav.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
testbench_behav.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
testbench_behav1.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
tridoracpu.xpr	lib,examples: changes for new register address mapping	2026-01-28 01:15:16 +01:00