373 lines
18 KiB
Text
373 lines
18 KiB
Text
#========================================================================
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# openCologne * NLnet-sponsored open-source design ware for GateMate
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#------------------------------------------------------------------------
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# Copyright (C) 2024 Chili.CHIPS*ba
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# https://opensource.org/license/bsd-3-clause
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#------------------------------------------------------------------------
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# Description:
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# Gatemate E1 evaluation board hardware pin constraints
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# file: GateMateA1-EVB.ccf
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## file: GateMateA1-EVB.ccf
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##
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## Gatemate A1-EVB Olimex board hardware pin constraints
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## #######################################################
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# Format:
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# <pin-direction> "<pin-name>" Loc = "<pin-location>" | <opt.-constraints>;
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# Net "<pin-name>" Loc = "<pin-location>" | <opt.-constraints>;
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#
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# Additional constraints can be appended using the pipe symbol.
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# Files are read line by line. Text after the hash symbol is ignored.
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#
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# Available pin directions:
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#
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# Pin_in
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# defines an input pin
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# Pin_out
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# defines an output pin
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# Pin_inout
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# defines a bidirectional pin
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#
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# Available pin constraints:
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#
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# SCHMITT_TRIGGER={true,false}
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# enables or disables schmitt trigger (hysteresis) option
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# PULLUP={true,false}
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# enables or disables I/O pullup resistor of nominal 50kOhm
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# PULLDOWN={true,false}
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# enables or disables I/O pulldown resistor of nominal 50kOhm
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# KEEPER={true,false}
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# enables or disables I/O keeper option
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# SLEW={slow,fast}
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# sets slew rate to slow or fast
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# DRIVE={3,6,9,12}
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# sets output drive strength to 3mA..12mA
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# DELAY_OBF={0..15}
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# adds an additional delay of n * nominal 50ps to output signal
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# DELAY_IBF={0..15}
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# adds an additional delay of n * nominal 50ps to input signal
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# FF_IBF={true,false}
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# enables or disables placing of FF in input buffer, if possible
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# FF_OBF={true,false}
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# enables or disables placing of FF in output buffer, if possible
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# LVDS_BOOST={true,false}
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# enables increased LVDS output current of 6.4mA (default: 3.2mA)
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# LVDS_TERM={true,false}
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# enables on-chip LVDS termination resistor of nominal 100Ohm, in output mode only
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#
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# Global IO constraints can be set with the default_GPIO statement. It can be
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# overwritten by individual settings for specific GPIOs, e.g.:
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# default_GPIO | DRIVE=3; # sets all output strengths to 3mA, unless overwritten
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#========================================================================
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# GPIO Configuration - Free Bank Selectable Voltage
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# Bank Selectable VDD 1.2V/1.8V/2.5V/User PWR_Supply
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#========================================================================
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# Depending on how you turn the Olimex Board, the orientation of the pins is flipped
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# If you turn the board so that you can read the Olimex logo and the VGA Port is to the left then the upper row is GND, NA_B..
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# And the lower row is VDD_NA, NA_A... from left to right
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#
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# If you turn the board so that the VGA Port is pointing up, then the VDD_NA, NA_A pins are to the left, like on the picture of the extension below
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# This is the case for the Bank_NA1, Bank_NB1 and Bank_EB1
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#========================================================================
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# Bank NA1
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#========================================================================
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# Upper Row
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# TOP LEFT PIN IS GND
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Net "NA_B0" Loc = "IO_NA_B0";
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Net "NA_B1" Loc = "IO_NA_B1";
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Net "NA_B2" Loc = "IO_NA_B2";
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Net "NA_B3" Loc = "IO_NA_B3"; # Bank_NA1
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Net "NA_B4" Loc = "IO_NA_B4"; # ____________
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Net "NA_B5" Loc = "IO_NA_B5"; # VDD_NA ------- | 1 2 | -------- GND
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Net "NA_B6" Loc = "IO_NA_B6"; # NA_A0 ------- | 3 4 | -------- NA_B0
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Net "NA_B7" Loc = "IO_NA_B7"; # NA_A1 ------- | 5 6 | -------- NA_B1
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Net "NA_B8" Loc = "IO_NA_B8"; # NA_A2 ------- | 7 8 | -------- NA_B2
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# ------------------------- # # NA_A3 ------- | 9 10 | -------- NA_B3
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# Lower Row # NA_A4 ------- | 11 12 | -------- NA_B4
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# BOTTOM LEFT PIN IS VDD # NA_A5 ------- | 13 14 | -------- NA_B5
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Net "NA_A0" Loc = "IO_NA_A0"; # NA_A6 ------- | 15 16 | -------- NA_B6
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Net "NA_A1" Loc = "IO_NA_A1"; # NA_A7 ------- | 17 18 | -------- NA_B7
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Net "NA_A2" Loc = "IO_NA_A2"; # NA_A8 ------- | 19 20 | -------- NA_B8
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Net "NA_A3" Loc = "IO_NA_A3"; # ____________
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Net "NA_A4" Loc = "IO_NA_A4";
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Net "NA_A5" Loc = "IO_NA_A5";
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Net "NA_A6" Loc = "IO_NA_A6";
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Net "NA_A7" Loc = "IO_NA_A7";
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Net "NA_A8" Loc = "IO_NA_A8";
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#========================================================================
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# Bank NB1
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#========================================================================
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# Upper Row
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# TOP LEFT PIN IS GND
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Net "NB_B0" Loc = "IO_NB_B0";
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Net "NB_B1" Loc = "IO_NB_B1";
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Net "NB_B2" Loc = "IO_NB_B2";
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Net "NB_B3" Loc = "IO_NB_B3"; # Bank_NB1
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Net "NB_B4" Loc = "IO_NB_B4"; # ____________
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Net "NB_B5" Loc = "IO_NB_B5"; # VDD_NA ------- | 1 2 | -------- GND
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Net "NB_B6" Loc = "IO_NB_B6"; # NB_A0 ------- | 3 4 | -------- NB_B0
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Net "NB_B7" Loc = "IO_NB_B7"; # NB_A1 ------- | 5 6 | -------- NB_B1
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Net "NB_B8" Loc = "IO_NB_B8"; # NB_A2 ------- | 7 8 | -------- NB_B2
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# --------------------------# # NB_A3 ------- | 9 10 | -------- NB_B3
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# Lower Row # NB_A4 ------- | 11 12 | -------- NB_B4
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# BOTTOM LEFT PIN IS VDD # NB_A5 ------- | 13 14 | -------- NB_B5
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Net "NB_A0" Loc = "IO_NB_A0"; # NB_A6 ------- | 15 16 | -------- NB_B6
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Net "NB_A1" Loc = "IO_NB_A1"; # NB_A7 ------- | 17 18 | -------- NB_B7
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Net "NB_A2" Loc = "IO_NB_A2"; # NB_A8 ------- | 19 20 | -------- NB_B8
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Net "NB_A3" Loc = "IO_NB_A3"; # ____________
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Net "NB_A4" Loc = "IO_NB_A4";
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Net "NB_A5" Loc = "IO_NB_A5";
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Net "NB_A6" Loc = "IO_NB_A6";
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Net "NB_A7" Loc = "IO_NB_A7";
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Net "NB_A8" Loc = "IO_NB_A8";
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#========================================================================
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# BANK_EB1
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#========================================================================
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# Upper Row
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# TOP LEFT PIN IS GND
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Net "EB_B0" Loc = "IO_EB_B0";
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Net "EB_B1" Loc = "IO_EB_B1";
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Net "EB_B2" Loc = "IO_EB_B2";
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Net "EB_B3" Loc = "IO_EB_B3"; # Bank_EB1
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Net "EB_B4" Loc = "IO_EB_B4"; # _____________
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Net "EB_B5" Loc = "IO_EB_B5"; # VDD_NA ------- | 1 2 | -------- GND
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Net "EB_B6" Loc = "IO_EB_B6"; # EB_A0 ------- | 3 4 | -------- EB_B0
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Net "EB_B7" Loc = "IO_EB_B7"; # EB_A1 ------- | 5 6 | -------- EB_B1
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Net "EB_B8" Loc = "IO_EB_B8"; # EB_A2 ------- | 7 8 | -------- EB_B2
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# --------------------------# # EB_A3 ------- | 9 10 | -------- EB_B2
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# Lower Row # EB_A4 ------- | 11 12 | -------- EB_B2
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# BOTTOM LEFT PIN IS VDD # # EB_A5 ------- | 13 14 | -------- EB_B2
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Net "EB_A0" Loc = "IO_EB_A0"; # EB_A6 ------- | 15 16 | -------- EB_B2
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Net "EB_A1" Loc = "IO_EB_A1"; # EB_A7 ------- | 17 18 | -------- EB_B2
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Net "EB_A2" Loc = "IO_EB_A2"; # EB_a8 ------- | 19 20 | -------- EB_B2
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Net "EB_A3" Loc = "IO_EB_A3"; # _____________
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Net "EB_A4" Loc = "IO_EB_A4";
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Net "EB_A5" Loc = "IO_EB_A5";
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Net "EB_A6" Loc = "IO_EB_A6";
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Net "EB_A7" Loc = "IO_EB_A7";
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Net "EB_A8" Loc = "IO_EB_A8";
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#========================================================================
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# BANK_MISC1
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#========================================================================
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# BANK_MISC1 is the big one to the right of the board and the configuration + text-picture below is taking into account that you have
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# the Olimex board placed so that the BANK_MISC1 is on the right side(VGA Port is on the left side).
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#========================================================================
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# Left Row
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# TOP LEFT PIN IS 2.5V
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#Net "FPGA_SPI_FWD" Loc = "IO_WA_B5"
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Net "EA_A8" Loc = "IO_EA_A8";
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Net "EA_B8" Loc = "IO_EA_B8";
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Net "WB_A8" Loc = "IO_WB_A8";
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Net "WB_B8" Loc = "IO_WB_B8";
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Net "SB_B3" Loc = "IO_SB_B3";
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Net "SB_B2" Loc = "IO_SB_B2";
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Net "SB_A2" Loc = "IO_SB_A2";
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Net "SB_B1" Loc = "IO_SB_B1";
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Net "SB_A1" Loc = "IO_SB_A1";
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Net "SB_B0" Loc = "IO_SB_B0"; # MISC1
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Net "SB_A0" Loc = "IO_SB_A0"; # _____________
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Net "FPGA_RESET_IN" Loc = "RST_N"; # 2.5V ----------| 1 2 | -------- 1.8V
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# SECOND TO LAST PIN # FPGA_SPI_FWD - | 3 4 | -------- WC_B3
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# IS NET-(BANK_MISC1-PAD31) # # EA_A8 -------- | 5 6 | -------- WC_A3
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# BOTTOM LEFT PIN IS GND # # EA_B8 -------- | 7 8 | -------- WC_B2
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# --------------------------# # WB_A8 -------- | 9 10 | -------- WC_A2
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# Right Row # # WB_B8 -------- | 11 12 | -------- WC_B1
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# TOP RIGHT PIN IN 1.8V # # SB_B3 -------- | 13 14 | -------- WC_A1
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Net "WC_B3" Loc = "IO_WC_B3"; # SB_A3 -------- | 15 16 | -------- WC_B0
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Net "WC_A3" Loc = "IO_WC_A3"; # SB_B2 -------- | 17 18 | -------- WC_A0
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Net "WC_B2" Loc = "IO_WC_B2"; # SB_A2 -------- | 19 20 | -------- SER_CLK_N
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Net "WC_A2" Loc = "IO_WC_A2"; # SB_B1 -------- | 21 22 | -------- SER_CLK_P
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Net "WC_B1" Loc = "IO_WC_B1"; # SB_A1 -------- | 23 24 | -------- SER_TX_P
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Net "WC_A1" Loc = "IO_WC_A1"; # SB_B0 -------- | 25 26 | -------- SER_TX_N
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Net "WC_B0" Loc = "IO_WC_B0"; # SB_A0 -------- | 27 28 | -------- SER_RX_N
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Net "WC_A0" Loc = "IO_WC_A0"; # FPGA_RESET_IN | 29 30 | -------- SER_TX_P
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# CLK0 ----------| 31 32 | -------- CLK3
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# GND ----------| 33 34 | -------- GND
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## Serdes # _____________
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# Note!: Take in mind that SerDes is not working when VDD_CORE = 0.9V(Low power mode) because VDDSER and VDDSER_PLL have got minimum working voltage 0.95V!
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Net "SER_CLK_N" Loc = "IO_SER_CLK_N";
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Net "SER_CLK_P" Loc = "IO_SER_CLK_P";
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Net "SER_TX_P" Loc = "IO_SER_TX_P";
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Net "SER_TX_N" Loc = "IO_SER_TX_N";
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Net "SER_RX_N" Loc = "IO_SER_RX_N";
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Net "SER_RX_P" Loc = "IO_SER_RX_P";
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# SECOND TO LAST PIN IS NET-(BANK_MISC1-PAD32) #
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# BOTTOM RIGHT PIN IS GND # #
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#========================================================================
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# GPIO
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#========================================================================
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# Mostly used for RP2040, change the names to better describe function
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#========================================================================
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Net "GPIO0" Loc = "IO_SA_A0";
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Net "GPIO1" Loc = "IO_SA_B0";
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Net "GPIO2" Loc = "IO_SA_A1";
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Net "GPIO3" Loc = "IO_SA_B1";
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Net "GPIO4" Loc = "IO_SA_A2";
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Net "GPIO5" Loc = "IO_SA_B2";
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Net "GPIO6" Loc = "IO_SA_A3";
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Net "GPIO7" Loc = "IO_SA_B3";
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Net "GPIO8" Loc = "IO_SA_A4";
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Net "GPIO9" Loc = "IO_SA_B4";
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Net "GPIO10" Loc = "IO_SA_A5";
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Net "GPIO11" Loc = "IO_SA_B5";
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Net "GPIO14" Loc = "IO_SA_A7";
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Net "GPIO15" Loc = "IO_SA_B7";
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Net "GPIO21" Loc = "IO_SB_B8"; # GPIN1
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Net "GPIO26" Loc = "IO_SB_B4";
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Net "GPIO27" Loc = "IO_SB_A4";
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Net "GPIO28" Loc = "IO_SA_A8";
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Net "GPIO29" Loc = "IO_SA_B8";
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#========================================================================
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# Generaly used IO Pins
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#========================================================================
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# LED, 4 Clocks for PLL
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#========================================================================
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Net "FPGA_LED" Loc = "IO_SB_B6"; # FPGA LED
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Net "FPGA_BUT" Loc = "IO_SB_B7";
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Net "CLK0" Loc = "IO_SB_A8"; # CLK0
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Net "CLK3" Loc = "IO_SB_A5";
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Net "GPIO24" Loc = "IO_SB_A6"; # CLK2
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Net "GPIO23" Loc = "IO_SB_A7"; # CLK1
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#========================================================================
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# UART Interface
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#========================================================================
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# There is a mistake on the schematic, these need to be flipped as below
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#========================================================================
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Net "DBG_UART_RX" Loc = "IO_SA_A6"; # GPIO12
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Net "DBG_UART_TX" Loc = "IO_SA_B6"; # GPIO13
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#========================================================================
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# JTAG Interface
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#========================================================================
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Net "JTAG_LED" Loc = "IO_SB_B5"; # GPIO25
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Net "JTAG_TCK" Loc = "IO_WA_A5"; # GPIO18
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Net "JTAG_TMS" Loc = "IO_WA_B4"; # GPIO19
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Net "JTAG_TDI" Loc = "IO_WA_A4"; # GPIO16
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Net "JTAG_TDO" Loc = "IO_WA_B3"; # GPIO17
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#========================================================================
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# SPI Configuration
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#========================================================================
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Net "FPGA_SPI_CLK" Loc = "IO_WA_B8";
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Net "FPGA_SPI_CSN" Loc = "IO_WA_A8";
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Net "FPGA_SPI_D0" Loc = "IO_WA_B7";
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Net "FPGA_SPI_D1" Loc = "IO_WA_A7";
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Net "FPGA_SPI_D2" Loc = "IO_WA_B6";
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Net "FPGA_SPI_D3" Loc = "IO_WA_A6";
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Net "FPGA_SPI_FWD" Loc = "IO_WA_B5";
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#========================================================================
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# PS2 Pin Configuration
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#========================================================================
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NET "PS2_CLK" Loc = "IO_WB_A0";
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NET "PS2_DATA" Loc = "IO_WB_B0";
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#========================================================================
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# VGA Configuration
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#========================================================================
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# TODO: Change the values to arrays maybe?
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#========================================================================
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Net "VGA_HSync" Loc = "IO_WB_A1";
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Net "VGA_VSync" Loc = "IO_WB_B1";
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Net "VGA_Red_3" Loc = "IO_WB_A2";
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Net "VGA_Red_2" Loc = "IO_WB_B2";
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Net "VGA_Red_1" Loc = "IO_WB_A3";
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Net "VGA_Red_0" Loc = "IO_WB_B3";
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Net "VGA_Green_3" Loc = "IO_WB_A4";
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Net "VGA_Green_2" Loc = "IO_WB_B4";
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Net "VGA_Green_1" Loc = "IO_WB_A5";
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Net "VGA_Green_0" Loc = "IO_WB_B5";
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Net "VGA_Blue_3" Loc = "IO_WB_A6";
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Net "VGA_Blue_2" Loc = "IO_WB_B6";
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Net "VGA_Blue_1" Loc = "IO_WB_A7";
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Net "VGA_Blue_0" Loc = "IO_WB_B7";
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#========================================================================
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## PSRAM Configuration
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#========================================================================
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Net "PSRAM_CS" Loc = "IO_WC_A4";
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Net "PSRAM_SCLK" Loc = "IO_WC_B4";
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Net "PSRAM_DATA0" Loc = "IO_WC_A5";
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Net "PSRAM_DATA1" Loc = "IO_WC_B5";
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Net "PSRAM_DATA2" Loc = "IO_WC_A6";
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Net "PSRAM_DATA3" Loc = "IO_WC_B6";
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Net "PSRAM_DATA4" Loc = "IO_WC_A7";
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Net "PSRAM_DATA5" Loc = "IO_WC_B7";
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Net "PSRAM_DATA6" Loc = "IO_WC_A8";
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Net "PSRAM_DATA7" Loc = "IO_WC_B8";
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#========================================================================
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# UEXT
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#========================================================================
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# _______________
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Net "UEXT_TXD" Loc = "IO_EA_A0"; # 3.3V ----- | 1 -- -- 2 | ----- GND
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Net "UEXT_RXD" Loc = "IO_EA_B0"; # UEXT_TXD - | 3 -- -- 4 | -UEXT_RXD
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Net "UEXT_SCL" Loc = "IO_EA_A1"; # UEXT_SCL - | 5 -- -- 6 | -UEXT_SDA
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Net "UEXT_SDA" Loc = "IO_EA_B1"; # UEXT_MISCO | 7 -- -- 8 | -UEXT_MOSI
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Net "UEXT_MISO" Loc = "IO_EA_A2"; # UEXT_SCK - | 9 -- --10 | -UEXT_CS
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Net "UEXT_MOSI" Loc = "IO_EA_B2"; # _______________
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Net "UEXT_SCK" Loc = "IO_EA_A3";
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Net "UEXT_CS" Loc = "IO_EA_B3";
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#========================================================================
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# PMOD
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#========================================================================
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# ___________
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Net "PMOD_1" Loc = "IO_EA_A4"; # | 1 7 |
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Net "PMOD_7" Loc = "IO_EA_B4"; # | 2 8 |
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Net "PMOD_2" Loc = "IO_EA_A5"; # | 3 9 |
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Net "PMOD_8" Loc = "IO_EA_B5"; # | 4 10 |
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Net "PMOD_3" Loc = "IO_EA_A6"; # GND -| 5 11 | --- GND
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Net "PMOD_9" Loc = "IO_EA_B6"; # 3-3V-| 6 12 | --- 3.3V
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Net "PMOD_4" Loc = "IO_EA_B7"; # ___________
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Net "PMOD_10" Loc = "IO_EA_A7";
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#========================================================================
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# End of hardware constraints GateMateA1-EVB.ccf
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#========================================================================
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