slederer 0f72080c56 tridoracpu: experimented with synthesis options again ... - workaround for an apparent bug with LOAD address generation at offsets >= 3584 - updated bitstream URL		2025-10-26 00:27:34 +02:00
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tridoracpu.srcs	tdraudio: add irq_enable flag, add pcmaudio library	2025-10-07 00:37:53 +02:00
sdspi_testbench_behav.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
testbench_behav.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
testbench_behav1.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
tridoracpu.xpr	tridoracpu: experimented with synthesis options again	2025-10-26 00:27:34 +02:00