a671a66276
examples: removed 5cubes due to unclear licensing add stuff to gitignore, licenses, README import Vivado project
46 lines
1.1 KiB
Verilog
46 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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// taken from https://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
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// modified for one read/write-port and one read-only-port,
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/// A parameterized, inferable, true dual-port, dual-clock block RAM in Verilog.
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module bram_tdp #(
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parameter DATA = 72,
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parameter ADDR = 10
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) (
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// Port A
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input wire a_clk,
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input wire a_rd,
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input wire a_wr,
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input wire [ADDR-1:0] a_addr,
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input wire [DATA-1:0] a_din,
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output reg [DATA-1:0] a_dout,
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// Port B
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input wire b_clk,
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input wire [ADDR-1:0] b_addr,
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output reg [DATA-1:0] b_dout,
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input wire b_rd
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);
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// Shared memory
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reg [DATA-1:0] mem [(2**ADDR)-1:0];
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wire a_en = a_rd || a_wr;
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// Port A
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always @(posedge a_clk) begin
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if(a_en)
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begin
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if(a_wr)
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mem[a_addr] <= a_din;
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else if(a_rd)
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a_dout <= mem[a_addr];
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end
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end
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// Port B
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always @(posedge b_clk) begin
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if(b_rd)
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b_dout <= mem[b_addr];
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end
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endmodule
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