Tridora-CPU/tridoracpu
2025-03-09 23:51:22 +01:00
..
tridoracpu.srcs tridoracpu: add missing xci file for the DRAM controller 2025-03-09 23:51:22 +01:00
sdspi_testbench_behav.wcfg import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
testbench_behav.wcfg import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
testbench_behav1.wcfg import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
tridoracpu.xpr update Vivado project file 2024-12-27 03:02:11 +01:00