slederer a441e7e042 import Vivado project, rearrange Verilog sources		2024-09-27 22:14:57 +02:00
..
tridoracpu.srcs	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
sdspi_testbench_behav.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
testbench_behav.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
testbench_behav1.wcfg	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00
tridoracpu.xpr	import Vivado project, rearrange Verilog sources	2024-09-27 22:14:57 +02:00