xilinx.com
xci
unknown
1.0
mig_dram_0
0
0
0
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
false
100000000
100000000
0
0
0.000
0
0
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
false
100000000
100000000
0
0
0.000
0
0
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
false
100000000
100000000
0
0
0.000
0
0
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
false
100000000
100000000
0
0
0.000
0
0
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
false
100000000
100000000
0
0
0.000
0
0
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
false
100000000
100000000
0
0
0.000
0
0
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
false
100000000
100000000
0
0
0.000
0
0
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
false
100000000
100000000
0
0
0.000
false
100000000
100000000
0
0
0.000
0
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
TDM
8
false
11
11
true
true
8
COMPONENTS
ROW_COLUMN_BANK
Single
1250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
0
false
100000000
100000000
0
0
0.000
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
32
32
32
4
1048576
32
4
1048576
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
8
2
OFF
1
OFF
100.0
FALSE
8
3
1
1
1
8
OFF
1
1
1
8
OFF
14
1
1
1
2
1
DDR3
FALSE
10.0
FALSE
10
FALSE
10
FALSE
10
FALSE
10
1200.0
0.000
ACTIVE_LOW
29
1
8
18
OFF
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
18
1
1
DIFF
FALSE
0
32
32
32
4
1048576
32
4
1048576
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
8
2
OFF
1
OFF
100.0
FALSE
8
3
1
1
1
8
OFF
1
1
1
8
OFF
14
1
1
1
2
1
DDR3
FALSE
10.0
FALSE
10
FALSE
10
FALSE
10
FALSE
10
1200.0
0.000
ACTIVE_LOW
29
1
8
18
OFF
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
18
1
1
DIFF
FALSE
0
32
32
32
4
1048576
32
4
1048576
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
8
2
OFF
1
OFF
100.0
FALSE
8
3
1
1
1
8
OFF
1
1
1
8
OFF
14
1
1
1
2
1
DDR3
FALSE
10.0
FALSE
10
FALSE
10
FALSE
10
FALSE
10
1200.0
0.000
ACTIVE_LOW
29
1
8
18
OFF
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
18
1
1
DIFF
FALSE
0
32
32
32
4
1048576
32
4
1048576
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
8
2
OFF
1
OFF
100.0
FALSE
8
3
1
1
1
8
OFF
1
1
1
8
OFF
14
1
1
1
2
1
DDR3
FALSE
10.0
FALSE
10
FALSE
10
FALSE
10
FALSE
10
1200.0
0.000
ACTIVE_LOW
29
1
8
18
OFF
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
18
1
1
DIFF
FALSE
0
32
32
32
4
1048576
32
4
1048576
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
8
2
OFF
1
OFF
100.0
FALSE
8
3
1
1
1
8
OFF
1
1
1
8
OFF
14
1
1
1
2
1
DDR3
FALSE
10.0
FALSE
10
FALSE
10
FALSE
10
FALSE
10
1200.0
0.000
ACTIVE_LOW
29
1
8
18
OFF
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
18
1
1
DIFF
FALSE
0
32
32
32
4
1048576
32
4
1048576
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
8
2
OFF
1
OFF
100.0
FALSE
8
3
1
1
1
8
OFF
1
1
1
8
OFF
14
1
1
1
2
1
DDR3
FALSE
10.0
FALSE
10
FALSE
10
FALSE
10
FALSE
10
1200.0
0.000
ACTIVE_LOW
29
1
8
18
OFF
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
18
1
1
DIFF
FALSE
0
32
32
32
4
1048576
32
4
1048576
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
8
2
OFF
1
OFF
100.0
FALSE
8
3
1
1
1
8
OFF
1
1
1
8
OFF
14
1
1
1
2
1
DDR3
FALSE
10.0
FALSE
10
FALSE
10
FALSE
10
FALSE
10
1200.0
0.000
ACTIVE_LOW
29
1
8
18
OFF
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
18
1
1
DIFF
FALSE
0
32
32
32
4
1048576
32
4
1048576
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
8
8
2
OFF
1
OFF
100.0
FALSE
8
3
1
1
1
8
OFF
1
1
1
8
OFF
14
1
1
1
2
1
DDR3
FALSE
10.0
FALSE
10
FALSE
10
FALSE
10
FALSE
10
1200.0
0.000
ACTIVE_LOW
29
1
8
18
OFF
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
18
1
1
DIFF
FALSE
0
0
28
32
32
4
1048576
128
2
268435456
8
3
1
1
1
8
OFF
1
1
1
8
1
OFF
14
1
1
1
2
1
28
3
1
1
1
16
OFF
2
1
2
16
1
OFF
14
1
1
1
4
1
8
8
2
OFF
1
OFF
83333333
FALSE
8
3
1
1
1
8
OFF
1
1
1
8
OFF
14
1
1
1
2
1
DDR3
FALSE
10.0
FALSE
10
FALSE
10
FALSE
10
FALSE
10
666
1
0.000
ACTIVE_LOW
29
1
8
18
OFF
1
NOBUF
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
1
18
OFF
1
1
1
8
1
29
1
29
2
1
18
1
1
NOBUF
INTERNAL
FALSE
0
Custom
mig_dram_0
Custom
Custom
mig_b.prj
artix7
digilentinc.com:arty-a7-35:part0:1.0
xc7a35ti
csg324
VERILOG
MIXED
-1L
I
TRUE
TRUE
IP_Flow
1
TRUE
.
.
2020.1
OUT_OF_CONTEXT