clk clk tx_data[7:0] tx_data[7:0] rx_data[7:0] rx_data[7:0] rx_shifter[7:0] rx_shifter[7:0] tx_shifter[7:0] tx_shifter[7:0] tx_fifo_out[7:0] tx_fifo_out[7:0] tx_fifo_rd_en tx_fifo_rd_en tx_fifo_wr_en tx_fifo_wr_en rx_fifo_wr_en rx_fifo_wr_en rx_bit_recvd rx_bit_recvd tail_x[4:0] tail_x[4:0] head_x[4:0] head_x[4:0] tx_ready tx_ready tx_empty tx_empty rx_avail rx_avail tx_write tx_write rx_read rx_read ctrl_write ctrl_write rx_filter_en rx_filter_en txrx_en txrx_en spiclk_div_wr spiclk_div_wr spi_clk_on spi_clk_on spiclk_f_en spiclk_f_en spi_clk_f_on spi_clk_f_on sd_cs_n sd_cs_n #DCDCDC true sd_mosi sd_mosi #00FFFF true sd_miso sd_miso sd_sck sd_sck #FFFF00 true xcvr_on xcvr_on hphase_start hphase_start #F0E68C true clk_phase[1:0] clk_phase[1:0] #D2691E true running running xcvr_bitcount[3:0] xcvr_bitcount[3:0] spi_clk_count[6:0] spi_clk_count[6:0] spi_clk_div[6:0] spi_clk_div[6:0]