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tdraudio-pcm #3

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slederer merged 14 commits from tdraudio-pcm into main 2025-10-13 00:42:14 +02:00
Conversation 0 Commits 14 Files changed 15 +59 -12
2 changed files with 59 additions and 12 deletions
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61
tridoracpu/tridoracpu.srcs/tdraudio.v
View file

@ -18,6 +18,19 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
localparam TDRAU_REG_CLK = 1; /* clock divider register */
localparam TDRAU_REG_AMP = 2; /* amplitude (volume) register */
// localparam LFSR_WIDTH = 15;
// localparam LFSR_TAP_IDX_1 = 3;
// localparam LFSR_TAP_IDX_2 = 0;
// localparam LFSR_INIT = 'h7672;
// localparam LFSR_WIDTH = 18;
// localparam LFSR_TAP_IDX_1 = 17;
// localparam LFSR_TAP_IDX_2 = 10;
// localparam LFSR_INIT = 'h3CBE6;
localparam LFSR_WIDTH = 23;
localparam LFSR_INIT = 'h1;
reg channel_enable;
reg [CLOCK_DIV_WIDTH-1:0] clock_div;
reg [CLOCK_DIV_WIDTH-1:0] div_count;
@ -25,8 +38,12 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
reg [AMP_WIDTH-1:0] amp_start;
reg [AMP_WIDTH-1:0] amp_out;
reg noise_enable;
reg [LFSR_WIDTH-1:0] lfsr;
wire [AMP_WIDTH-1:0] noise_out;
//assign rd_data = {{DATA_WIDTH-8-CLOCK_DIV_WIDTH{1'b0}}, div_count, {7{1'b0}}, channel_enable};
assign rd_data = {8'b0, amp_start, {7{1'b0}}, channel_enable};
assign rd_data = {8'b0, amp_start, {6{1'b0}}, noise_enable, channel_enable};
assign amp_val = amp_out;
assign running = channel_enable;
@ -70,10 +87,38 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
div_count <= div_count - 1; // else just decrement it
end
else
if (wr_en && (reg_sel == TDRAU_REG_CLK))
div_count <= 1; // start cycle in next clock tick
if (wr_en && (reg_sel == TDRAU_REG_CLK)) // when setting divider,
div_count <= 1; // start cycle on next clock tick
end
/* noise enable flag */
always @(posedge clk)
begin
if(reset)
noise_enable <= 0;
else if (wr_en && (reg_sel == TDRAU_REG_CTL))
noise_enable <= wr_data[1];
end
/* noise generator (Linear Feedback Shift Register) */
always @(posedge clk)
begin
if (reset)
lfsr <= LFSR_INIT;
else
if (wr_en && (reg_sel == TDRAU_REG_CTL) && wr_data[1])
lfsr <= LFSR_INIT;
else
if (channel_enable && noise_enable)
if (div_count == 0)
//lfsr <= { lfsr[LFSR_TAP_IDX_1] ^ lfsr[LFSR_TAP_IDX_2], lfsr[LFSR_WIDTH-1:1] };
// shift width and tap bits taken from https://github.com/jotego/jtopl
lfsr <= { lfsr[LFSR_WIDTH-2:0], lfsr[22] ^ lfsr[9] ^ lfsr[8] ^ lfsr[0]};
end
assign noise_out = lfsr[0] ? amp_start : ~amp_start;
/* amplitude out */
always @(posedge clk)
begin
@ -83,11 +128,17 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
amp_phase <= 1;
end
else
if (channel_enable && (div_count == 0)) // invert amplitude on clock tick
if (channel_enable)
begin
amp_out <= amp_phase ? amp_start : ~amp_start;
if (div_count == 0) // invert amplitude on clock tick
begin
amp_out <= noise_enable ? noise_out :
amp_phase ? amp_start : ~amp_start;
amp_phase <= ~amp_phase;
end
end
else
amp_out <= 0;
// reset phase bit when enabling the channel
if (wr_en && (reg_sel == TDRAU_REG_CTL) && wr_data[0])

8
tridoracpu/tridoracpu.xpr
View file

@ -358,9 +358,7 @@
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, lowering multiplier threshold of inference into DSP blocks, moving shift register into BRAM, applying lower thresholds for use of carry chain in comparators and also area optimized mux optimizations" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Flow_AreaOptimized_medium" Flow="Vivado Synthesis 2024">
<Desc>Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, lowering multiplier threshold of inference into DSP blocks, moving shift register into BRAM, applying lower thresholds for use of carry chain in comparators and also area optimized mux optimizations</Desc>
</StratHandle>
<StratHandle Name="Flow_AreaOptimized_medium" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design">
<Option Id="ControlSetOptThreshold">1</Option>
<Option Id="Directive">2</Option>
@ -383,9 +381,7 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>