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tdraudio-pcm #3

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slederer merged 14 commits from tdraudio-pcm into main 2025-10-13 00:42:14 +02:00
Conversation 0 Commits 14 Files changed 15 +45 -18
2 changed files with 45 additions and 18 deletions
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45
tridoracpu/tridoracpu.srcs/tdraudio.v
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@ -113,28 +113,45 @@ module tdraudio #(DATA_WIDTH=32) (
localparam CLOCK_DIV_WIDTH = 22; localparam CLOCK_DIV_WIDTH = 22;
localparam AMP_WIDTH = 16; localparam AMP_WIDTH = 16;
localparam DAC_WIDTH = 18;
wire chan_sel = io_addr[6:2]; wire [4:0] chan_sel = io_addr[6:2];
wire [1:0] reg_sel = io_addr[1:0]; wire [1:0] reg_sel = io_addr[1:0];
wire [AMP_WIDTH-1:0] chan0_amp; wire [AMP_WIDTH-1:0] chan0_amp;
wire [DATA_WIDTH-1:0] chan0_rd_data; wire [DATA_WIDTH-1:0] chan0_rd_data;
wire chan0_running; wire chan0_running;
wire chan0_sel = chan_sel == 0; wire chan0_sel = chan_sel == 5'd0;
wire chan0_rd_en = chan0_sel && rd_en; wire chan0_rd_en = chan0_sel && rd_en;
wire chan0_wr_en = chan0_sel && wr_en; wire chan0_wr_en = chan0_sel && wr_en;
wire [AMP_WIDTH-1:0] chan1_amp; wire [AMP_WIDTH-1:0] chan1_amp;
wire [DATA_WIDTH-1:0] chan1_rd_data; wire [DATA_WIDTH-1:0] chan1_rd_data;
wire chan1_running; wire chan1_running;
wire chan1_sel = chan_sel == 1; wire chan1_sel = chan_sel == 5'd1;
wire chan1_rd_en = chan1_sel && rd_en; wire chan1_rd_en = chan1_sel && rd_en;
wire chan1_wr_en = chan1_sel && wr_en; wire chan1_wr_en = chan1_sel && wr_en;
wire running = chan0_running || chan1_running; wire [AMP_WIDTH-1:0] chan2_amp;
wire [DATA_WIDTH-1:0] chan2_rd_data;
wire chan2_running;
wire chan2_sel = chan_sel == 5'd2;
wire chan2_rd_en = chan2_sel && rd_en;
wire chan2_wr_en = chan2_sel && wr_en;
wire [AMP_WIDTH-1:0] chan3_amp;
wire [DATA_WIDTH-1:0] chan3_rd_data;
wire chan3_running;
wire chan3_sel = chan_sel == 5'd3;
wire chan3_rd_en = chan3_sel && rd_en;
wire chan3_wr_en = chan3_sel && wr_en;
wire running = chan0_running || chan1_running || chan2_running || chan3_running;
assign rd_data = chan0_sel ? chan0_rd_data : assign rd_data = chan0_sel ? chan0_rd_data :
chan1_sel ? chan1_rd_data : chan1_sel ? chan1_rd_data :
chan2_sel ? chan2_rd_data :
chan3_sel ? chan3_rd_data :
{DATA_WIDTH{1'b1}}; {DATA_WIDTH{1'b1}};
wavegen chan0(clk, reset, reg_sel, wavegen chan0(clk, reset, reg_sel,
@ -147,9 +164,19 @@ module tdraudio #(DATA_WIDTH=32) (
chan1_rd_en, chan1_wr_en, chan1_rd_en, chan1_wr_en,
chan1_amp, chan1_running); chan1_amp, chan1_running);
reg [AMP_WIDTH:0] deltasigma_acc; // one extra bit wavegen chan2(clk, reset, reg_sel,
wire [AMP_WIDTH:0] amp_sum = chan0_amp + chan1_amp; // also one overflow bit here chan2_rd_data, wr_data,
wire [AMP_WIDTH-1:0] amp_sum_scaled = amp_sum[AMP_WIDTH:1]; // shifted right to scale down chan2_rd_en, chan2_wr_en,
chan2_amp, chan2_running);
wavegen chan3(clk, reset, reg_sel,
chan3_rd_data, wr_data,
chan3_rd_en, chan3_wr_en,
chan3_amp, chan3_running);
reg [DAC_WIDTH:0] deltasigma_acc; // one extra bit
wire [DAC_WIDTH:0] amp_sum = chan0_amp + chan1_amp + chan2_amp + chan3_amp; // also one overflow bit here
//wire [AMP_WIDTH-1:0] amp_sum_scaled = amp_sum[DAC_WIDTH-2:2]; // shifted right to scale down
assign gain_sel = 1; // gain select: 0 -> 12dB, 1 -> 6dB assign gain_sel = 1; // gain select: 0 -> 12dB, 1 -> 6dB
assign shutdown_n = running; assign shutdown_n = running;
@ -161,9 +188,9 @@ module tdraudio #(DATA_WIDTH=32) (
deltasigma_acc <= 0; deltasigma_acc <= 0;
else else
if (running) if (running)
deltasigma_acc <= deltasigma_acc[AMP_WIDTH-1:0] + amp_sum_scaled; deltasigma_acc <= deltasigma_acc[DAC_WIDTH-1:0] + amp_sum;
end end
/* 1-bit audio output */ /* 1-bit audio output */
assign pdm_out = deltasigma_acc[AMP_WIDTH]; assign pdm_out = deltasigma_acc[DAC_WIDTH];
endmodule endmodule

18
tridoracpu/tridoracpu.xpr
View file

@ -356,16 +356,14 @@
</Simulator> </Simulator>
</Simulators> </Simulators>
<Runs Version="1" Minor="22"> <Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, lowering multiplier threshold of inference into DSP blocks, moving shift register into BRAM, applying lower thresholds for use of carry chain in comparators and also area optimized mux optimizations" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Flow_PerfOptimized_high" Flow="Vivado Synthesis 2024"/> <StratHandle Name="Flow_AreaOptimized_medium" Flow="Vivado Synthesis 2024">
<Desc>Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, lowering multiplier threshold of inference into DSP blocks, moving shift register into BRAM, applying lower thresholds for use of carry chain in comparators and also area optimized mux optimizations</Desc>
</StratHandle>
<Step Id="synth_design"> <Step Id="synth_design">
<Option Id="Directive">7</Option> <Option Id="ControlSetOptThreshold">1</Option>
<Option Id="FsmExtraction">1</Option> <Option Id="Directive">2</Option>
<Option Id="KeepEquivalentRegisters">1</Option>
<Option Id="NoCombineLuts">1</Option>
<Option Id="ResourceSharing">2</Option>
<Option Id="ShregMinSize">5</Option>
</Step> </Step>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -385,7 +383,9 @@
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"/> <Step Id="opt_design"/>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>