changemem: program to change heap/stack size in program files

sasm: set stack size correctly
vga framebuffer: use 640x480@60Hz video timings
2025-07-05 00:05:44 +02:00 · 2025-07-03 00:45:26 +02:00 · 2025-06-22 00:33:02 +02:00
7 changed files with 216 additions and 19 deletions
--- a/pcomp/Makefile
+++ b/pcomp/Makefile
@ -31,6 +31,7 @@ nativeprogs: nativecomp
 	$(PCOMP) ../progs/partmgr.pas
 	$(PCOMP) ../progs/xfer.pas
 	$(PCOMP) ../progs/recover.pas
+	$(PCOMP) ../progs/changemem.pas
 	$(SASM) ../lib/rommon.s
 	$(SASM) -A ../lib/rommon.s ../lib/rom.mem

--- a/pcomp/make.bat
+++ b/pcomp/make.bat
@ -28,6 +28,7 @@ py pcomp.py ..\progs\dumpdir.pas
 py pcomp.py ..\progs\partmgr.pas
 py pcomp.py ..\progs\xfer.pas
 py pcomp.py ..\progs\recover.pas
+py pcomp.py ..\progs\changemem.pas
 sasm ..\lib\rommon.s
 sasm -A ..\lib\rommon.s ..\lib\rom.mem

--- a/pcomp/sasm.pas
+++ b/pcomp/sasm.pas
@ -1,7 +1,7 @@
 (* Copyright 2021-2024 Sebastian Lederer. See the file LICENSE.md for details *)
 {$MODE objfpc}
 {$H600}
-{$S4}
+{$S32}
 program sasm;
 {$!}{$ifdef FPC}uses math,crt;{$endif}
 {$R+}
--- a/progs/changemem.pas
+++ b/progs/changemem.pas
@ -0,0 +1,173 @@
+program changemem;
+const ProgramMagic = $00100AFE;
+type ProgramHeader = record
+		magic:integer;
+		heapSize:integer;
+		stackSize:integer;
+		mainPtr:integer;
+	end;
+
+var filename:string;
+    h:ProgramHeader;
+
+procedure showHex(value:integer);
+var i:integer;
+    digit:integer;
+    digits:array[1..8] of char;
+    ch:char;
+begin
+	for i := 1 to 8 do
+	begin
+		digit := value and 15;
+		value := value shr 4;
+
+		if digit < 10 then
+			ch := chr(digit + ord('0'))
+		else
+			ch := chr(digit - 10 + ord('A'));
+		digits[i] := ch;
+	end;
+	for i := 8 downto 1 do
+		write(digits[i]);
+end;
+
+procedure showValue(labl:string; value:integer);
+begin
+	write(labl:20, ' ');
+	write(value:8, ' (');
+	showHex(value);
+	writeln(')');
+end;
+
+procedure showHeader(var h:ProgramHeader);
+begin
+	showValue('heap size', h.heapSize);
+	showValue('stack size', h.stackSize);
+	showValue('main entry point', h.mainPtr);
+end;
+
+procedure readHeader(var filename:string;var h:ProgramHeader);
+var f:file;
+begin
+	writeln('reading file ', filename);
+	open(f, filename, ModeReadOnly);
+	if IOResult(f) <> 0 then
+	begin
+		writeln('Error opening file: ', ErrorStr(IOResult(f)));
+		halt;
+	end
+	else
+	begin
+		read(f, h);
+		if IOResult(f) <> 0 then
+		begin
+			writeln('Error reading header: ', ErrorStr(IOResult(f)));
+			halt;
+		end;
+		close(f);
+	end;
+end;
+
+procedure writeHeader(var filename:string;var h:ProgramHeader);
+var f:file;
+begin
+	writeln('writing file ', filename);
+	open(f, filename, ModeModify);
+	if IOResult(f) <> 0 then
+	begin
+		writeln('Error opening file: ', ErrorStr(IOResult(f)));
+		halt;
+	end
+	else
+	begin
+		write(f, h);
+		if IOResult(f) <> 0 then
+		begin
+			writeln('Error writing header: ', ErrorStr(IOResult(f)));
+			halt;
+		end;
+		close(f);	
+	end;
+end;
+
+procedure modifyHeader(var filename:string;var h:ProgramHeader);
+var done:boolean;
+    ch:char;
+    changed:boolean;
+
+	function getNewValue(descr:string):integer;
+	var buf:string;
+	    v,e:integer;
+	begin
+		getNewValue := 0;
+		write('New ',descr, ' size (decimal)> ');
+		readln(buf);
+		val(buf, v, e);
+		if(e > 0 ) or (v <= 0) then
+			writeln('invalid size')
+		else
+			getNewValue := v;
+	end;
+	
+	procedure changeStackSize;
+	var v:integer;
+	begin
+		v := getNewValue('stack');
+		if v > 0 then
+		begin
+			h.stackSize := v;
+			changed := true;
+		end;	
+	end;
+
+	procedure changeHeapSize;
+	var v:integer;
+	begin
+		v := getNewValue('heap');
+		if v > 0 then
+		begin
+			h.heapSize := v;
+			changed := true;
+		end;
+	end;
+
+begin
+	changed := false; done := false;
+
+	while not done do
+	begin
+		writeln(filename, ' header:');
+		showHeader(h);
+		writeln('Change H)eap size   Change S)tack size   eX)it');
+		write('> ');
+		read(ch);
+		writeln;
+		case upcase(ch) of
+		'S': changeStackSize;
+		'H': changeHeapSize;
+		'X': done := true;
+		else
+			writeln('invalid command');
+		end;
+	end;
+
+	if changed then
+		writeHeader(filename, h);
+end;
+
+begin
+	if ParamCount > 0 then
+		filename := ParamStr(1)
+	else
+	begin
+		write('File name> ');
+		readln(filename);
+	end;
+
+	readHeader(filename, h);
+
+	if h.magic <> ProgramMagic then
+		writeln('invalid magic value ', h.magic)
+	else
+		modifyHeader(filename, h);
+end.
--- a/tridoracpu/tridoracpu.srcs/vgafb.v
+++ b/tridoracpu/tridoracpu.srcs/vgafb.v
@ -6,8 +6,11 @@
 // Learn more at https://projectf.io

 //128K video memory is not enough for 640x480x4
-`define RES_640_400
+//`define RES_640_400
 //`define RES_1024_768
+// RES_640_480 mode displays 400 lines with 640x480/60 video timings,
+// adding blank lines at the bottom
+`define RES_640_480

 module display_timings #(
    H_RES=640,                      // horizontal resolution (pixels)
@ -126,6 +129,8 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
    localparam COLOR_WIDTH = 12;
    localparam PALETTE_WIDTH = 4;

+    localparam signed PIC_LINES = 400; // visible picture lines
+
    // Display Clocks
    wire pix_clk = CLK;                   // pixel clock
    wire clk_lock = 1;                  // clock locked?
@ -202,6 +207,18 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
        .V_BP(35),
        .H_POL(0),
        .V_POL(1)
+ `endif
+ `ifdef RES_640_480
+        .H_RES(640),               //     640      800     1280      1920
+        .V_RES(480),                //     480      600      720      1080
+        .H_FP(16),                 //      16       40      110        88
+        .H_SYNC(96),                //      96      128       40        44
+        .H_BP(48),                 //      48       88      220       148
+        .V_FP(10),                   //      10        1        5         4
+        .V_SYNC(2),                 //       2        4        5         5
+        .V_BP(33),                  //      33       23       20        36
+        .H_POL(0),                  //       0        1        1         1
+        .V_POL(0)                   //       0        1        1         1
 `endif
    )
    display_timings_inst (
@ -217,6 +234,8 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
        .o_sy(sy)
    );

+    wire pic_enable = (sy >= 0) && (sy < PIC_LINES);  // when to display pixels from VRAM
+
    wire [7:0] red;
    wire [7:0] green;
    wire [7:0] blue;
@ -288,7 +307,7 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
    // 12 bit RGB palette
    assign VGA_HS   = h_sync;
    assign VGA_VS   = v_sync;
-    assign VGA_R    = de ? color_data[11:8] : 4'b0;
-    assign VGA_G    = de ? color_data[7:4]  : 4'b0;
-    assign VGA_B    = de ? color_data[3:0]  : 4'b0;
+    assign VGA_R    = (pic_enable && de) ? color_data[11:8] : 4'b0;
+    assign VGA_G    = (pic_enable && de) ? color_data[7:4]  : 4'b0;
+    assign VGA_B    = (pic_enable && de) ? color_data[3:0]  : 4'b0;
 endmodule
--- a/tridoracpu/tridoracpu.xpr
+++ b/tridoracpu/tridoracpu.xpr
@ -351,7 +351,9 @@
  <Runs Version="1" Minor="22">
    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
        <Step Id="synth_design"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -361,9 +363,7 @@
    </Run>
    <Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" ParallelReportGen="true">
      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
        <Step Id="synth_design"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -371,21 +371,25 @@
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
      <RQSFiles/>
    </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Increase placer effort in the post-placement optimization phase, and disable timing relaxation in the router." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Best predicted directive for place_design." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Performance_RefinePlacement" Flow="Vivado Implementation 2020"/>
+        <StratHandle Name="Performance_Auto_1" Flow="Vivado Implementation 2024">
+          <Desc>Best predicted directive for place_design.</Desc>
+        </StratHandle>
        <Step Id="init_design"/>
-        <Step Id="opt_design"/>
+        <Step Id="opt_design">
+          <Option Id="Directive">0</Option>
+        </Step>
        <Step Id="power_opt_design"/>
        <Step Id="place_design">
-          <Option Id="Directive">7</Option>
+          <Option Id="Directive">20</Option>
        </Step>
        <Step Id="post_place_power_opt_design"/>
        <Step Id="phys_opt_design">
-          <Option Id="Directive">0</Option>
+          <Option Id="Directive">2</Option>
        </Step>
        <Step Id="route_design">
-          <Option Id="Directive">0</Option>
+          <Option Id="Directive">1</Option>
        </Step>
        <Step Id="post_route_phys_opt_design"/>
        <Step Id="write_bitstream">
@ -393,15 +397,13 @@
        </Step>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
      <RQSFiles/>
    </Run>
    <Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" ParallelReportGen="true">
      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
        <Step Id="init_design"/>
        <Step Id="opt_design"/>
        <Step Id="power_opt_design"/>
--- a/utils/tdrimg.py
+++ b/utils/tdrimg.py
@ -536,6 +536,7 @@ def create_image_with_stuff(imgfile):
    slotnr = putfile("../progs/editor.prog", None , f, part, partstart, slotnr)
    slotnr = putfile("../progs/xfer.prog", None , f, part, partstart, slotnr)
    slotnr = putfile("../progs/recover.prog", None , f, part, partstart, slotnr)
+    slotnr = putfile("../progs/changemem.prog", None , f, part, partstart, slotnr)

    listdir(f, part)
Author	SHA1	Message	Date
slederer	8c420dff75	changemem: program to change heap/stack size in program files	2025-07-05 00:05:44 +02:00
slederer	901a2b3e6d	sasm: set stack size correctly	2025-07-03 00:45:26 +02:00
slederer	ecff04a7a0	vga framebuffer: use 640x480@60Hz video timings - we still can only display 400 lines, so 80 blank lines are added at the bottom - we get square pixels this way and are hopefully more compatible with monitors and other devices like scan converters and capture cards	2025-06-22 00:33:02 +02:00