31 changed files with 751 additions and 805 deletions
--- a/.gitignore
+++ b/.gitignore
@ -2,7 +2,6 @@ pcomp/*.s
 progs/*.s
 tests/*.s
 examples/*.s
-!runtime.s
 *.o
 *.exe
 *.bin
@ -22,18 +21,14 @@ sine.pas
 graph1.pas
 graph2.pas
 chase.pas
-**/tridoracpu.cache/
-**/tridoracpu.hw/
-**/tridoracpu.ip_user_files/
-**/tridoracpu.runs/
-*.log
-*.jou
-**/mig_dram_0/_tmp/*
-**/mig_dram_0/doc/*
-**/mig_dram_0/mig_dram_0*
-**/mig_dram_0/xil_txt.*
-**/mig_dram_0/*.veo
-**/mig_dram_0/*.tcl
-**/mig_dram_0/*.xml
-**/mig_dram_0/*.v
-**/mig_dram_0/*.vhdl
+!runtime.s
+**/tridoracpu.*/
+rtl/arty-a7/mig_dram_0/_tmp/*
+rtl/arty-a7/mig_dram_0/doc/*
+rtl/arty-a7/mig_dram_0/mig_dram_0*
+rtl/arty-a7/mig_dram_0/xil_txt.*
+rtl/arty-a7/mig_dram_0/*.veo
+rtl/arty-a7/mig_dram_0/*.tcl
+rtl/arty-a7/mig_dram_0/*.xml
+rtl/arty-a7/mig_dram_0/*.v
+rtl/arty-a7/mig_dram_0/*.vhdl
--- a/README.md
+++ b/README.md
@ -6,7 +6,7 @@ Everything is as simple as possible while still being reasonably useful.
 Everything is open source, so you can read, understand and modify the whole system, hardware and software.

 ## Overview
- homebrew CPU
+- Homebrew CPU
 - Verilog FPGA SoC
 - 32-bit word-oriented stack machine architecture
 - running at 83 MHz on an Arty-A7 board with four clocks per instruction
@ -17,11 +17,11 @@ Everything is open source, so you can read, understand and modify the whole syst
 - minimal operating system
 - editor, compiler, assembler run natively
 - so you can develop programs directly on the machine
- small: CPU has 430 lines of Verilog, compiler ~9000 LoC
- compiler written in Pascal and can compile itself
- cross-compiler/-assembler can be compiled with FPC
- compiler does its own Pascal dialect with some restrictions and some extensions
- emulator available
+- small: CPU has 760 lines of verilog, compiler ~9000 LoC
+- Compiler written in Pascal and can compile itself
+- Cross-compiler/-assembler can be compiled with FPC
+- Compiler does its own Pascal dialect with some restrictions and some extensions
+- Emulator available

 ## Demo
 - (Video hello world)
@ -59,11 +59,3 @@ Everything is open source, so you can read, understand and modify the whole syst
 - most parts of the operating system are contained in the program image
 - file system is very primitive: only contiguous blocks, no subdirectories
 - simple shell reminiscent of TP3.0, edit, compile, run programs
-
-## Building the FPGA bitstream
- install Vivado (tested with 2024.1)
- install the package from your board in Vivado (Tools -> Vivado Store -> Boards)
- run the project creation script in Vivado (Tools -> Run TCL Script -> open "tridoracpu.tcl" in the **rtl/arty-a7 directory**)
- run synthesis, implementation and bitstream generation (Flow -> Generate Bitstream)
- program your device (Flow -> Open Hardware Manager), the bitstream file should be in **rtl/arty-a7/tridoracpu.runs/impl_1**
- the bitstream file for (temporarily) programming your device is named **top.bit**, the file for flashing your device is named **top.bin**
--- a/progs/editor.pas
+++ b/progs/editor.pas
@ -390,7 +390,8 @@ begin
 	if numMode then
 		isValidChar := isDigit(ch)
 	else
-		isValidChar := (ord(ch) >= 32)
+		isValidChar := (ord(ch) >= 32) and
+			(ord(ch) <> 127); (* don't want DEL character *)
 end;

 begin
@ -426,7 +427,7 @@ begin
 			c := chr(key);
 			l := length(strReturn);

-			if (c = #8) or (c = #127) then
+			if c = #8 then
 				doBackspace
 			else
 			if isValidChar(c) then
--- a/tridoracpu/tridoracpu.srcs/Arty-A7-35-Master.xdc
+++ b/tridoracpu/tridoracpu.srcs/Arty-A7-35-Master.xdc
--- a/rtl/arty-a7/Arty_C_mig.ucf
+++ b/rtl/arty-a7/Arty_C_mig.ucf
@ -0,0 +1,48 @@
+NET "ddr3_dq[0]"                             LOC = "K5"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[1]"                             LOC = "L3"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[2]"                             LOC = "K3"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[3]"                             LOC = "L6"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[4]"                             LOC = "M3"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[5]"                             LOC = "M1"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[6]"                             LOC = "L4"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[7]"                             LOC = "M2"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[8]"                             LOC = "V4"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[9]"                             LOC = "T5"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[10]"                            LOC = "U4"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[11]"                            LOC = "V5"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[12]"                            LOC = "V1"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[13]"                            LOC = "T3"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[14]"                            LOC = "U3"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dq[15]"                            LOC = "R3"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dm[0]"                             LOC = "L1"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dm[1]"                             LOC = "U1"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_dqs_p[0]"                          LOC = "N2"      |   IOSTANDARD = DIFF_SSTL135          ;                                 
+NET "ddr3_dqs_n[0]"                          LOC = "N1"      |   IOSTANDARD = DIFF_SSTL135          ;                                 
+NET "ddr3_dqs_p[1]"                          LOC = "U2"      |   IOSTANDARD = DIFF_SSTL135          ;                                 
+NET "ddr3_dqs_n[1]"                          LOC = "V2"      |   IOSTANDARD = DIFF_SSTL135          ;                                 
+NET "ddr3_addr[13]"                          LOC = "T8"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_addr[12]"                          LOC = "T6"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_addr[11]"                          LOC = "U6"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_addr[10]"                          LOC = "R6"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_addr[9]"                           LOC = "V7"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_addr[8]"                           LOC = "R8"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_addr[7]"                           LOC = "U7"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_addr[6]"                           LOC = "V6"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_addr[5]"                           LOC = "R7"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_addr[4]"                           LOC = "N6"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_addr[3]"                           LOC = "T1"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_addr[2]"                           LOC = "N4"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_addr[1]"                           LOC = "M6"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_addr[0]"                           LOC = "R2"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_ba[2]"                             LOC = "P2"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_ba[1]"                             LOC = "P4"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_ba[0]"                             LOC = "R1"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_ck_p[0]"                           LOC = "U9"      |   IOSTANDARD = DIFF_SSTL135          ;                                 
+NET "ddr3_ck_n[0]"                           LOC = "V9"      |   IOSTANDARD = DIFF_SSTL135          ;                                 
+NET "ddr3_ras_n"                             LOC = "P3"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_cas_n"                             LOC = "M4"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_we_n"                              LOC = "P5"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_reset_n"                           LOC = "K6"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_cke[0]"                            LOC = "N5"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_odt[0]"                            LOC = "R5"      |   IOSTANDARD = SSTL135               ;                                 
+NET "ddr3_cs_n[0]"                           LOC = "U8"      |   IOSTANDARD = SSTL135               ;                                 
--- a/tridoracpu/tridoracpu.srcs/mig_dram_0/mig_a.prj
+++ b/tridoracpu/tridoracpu.srcs/mig_dram_0/mig_a.prj
--- a/tridoracpu/tridoracpu.srcs/mig_dram_0/mig_b.prj
+++ b/tridoracpu/tridoracpu.srcs/mig_dram_0/mig_b.prj
--- a/rtl/arty-a7/sdspi_testbench_behav.wcfg
+++ b/rtl/arty-a7/sdspi_testbench_behav.wcfg
--- a/rtl/arty-a7/testbench_behav1.wcfg
+++ b/rtl/arty-a7/testbench_behav1.wcfg
--- a/rtl/arty-a7/tridoracpu.tcl
+++ b/rtl/arty-a7/tridoracpu.tcl
@ -0,0 +1,683 @@
+#*****************************************************************************************
+# Vivado (TM) v2020.1 (64-bit)
+#
+# tridoracpu.tcl: Tcl script for re-creating project 'tridoracpu'
+#
+# Generated by Vivado on Sat Sep 14 23:58:12 +0200 2024
+# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+
+# uncomment next two statements if you have never initialized the Xilinx Board Store
+# this will take quite some time
+#xhub::refresh_catalog [xhub::get_xstores xilinx_board_store]
+#xhub::install [xhub::get_xitems]
+
+# Set the reference directory for source file relative paths
+set origin_dir "change_this_to_your_rtl_directory"
+
+set xilinx_board_store_dir [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]]
+set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]]
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "tridoracpu"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "tridoracpu.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "${origin_dir}/arty-a7"]"
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a35ticsg324-1L
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+#set_property -name "board_part_repo_paths" -value "[file normalize "$xilinx_board_store_dir"]" -objects $obj
+set_property -name "board_part" -value "digilentinc.com:arty-a7-35:part0:1.0" -objects $obj
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "platform.board_id" -value "arty-a7-35" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "source_mgmt_mode" -value "DisplayOnly" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "4" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "4" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "4" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "4" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "4" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "4" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "4" -objects $obj
+set_property -name "webtalk.xsim_launch_sim" -value "537" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/src/uart.v"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Add local files from the original project (-no_copy_sources specified)
+set files [list \
+ [file normalize "${origin_dir}/src/cpuclk.v" ]\
+ [file normalize "${origin_dir}/src/display_clock.v" ]\
+ [file normalize "${origin_dir}/src/mem.v" ]\
+ [file normalize "${origin_dir}/src/stack.v" ]\
+ [file normalize "${origin_dir}/src/stackcpu.v" ]\
+ [file normalize "${origin_dir}/src/vgafb.v" ]\
+ [file normalize "${origin_dir}/src/top.v" ]\
+ [file normalize "${origin_dir}/src/testbench.v" ]\
+ [file normalize "${orig_proj_dir}/rom.mem" ]\
+ [file normalize "${orig_proj_dir}/mig_dram_0/mig_a.prj" ]\
+ [file normalize "${orig_proj_dir}/mig_dram_0/mig_b.prj" ]\
+ [file normalize "${origin_dir}/src/dram_bridge.v" ]\
+ [file normalize "${origin_dir}/src/sdspi.v" ]\
+ [file normalize "${origin_dir}/src/bram_tdp.v" ]\
+ [file normalize "${origin_dir}/src/palette.v" ]\
+ [file normalize "${origin_dir}/src/irqctrl.v" ]\
+ [file normalize "${origin_dir}/src/fifo.v" ]\
+ [file normalize "${origin_dir}/src/fifo_testbench.v" ]\
+ [file normalize "${origin_dir}/src/sdspi_testbench.v" ]\
+]
+set added_files [add_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+set file "$origin_dir/src/uart.v"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
+set_property -name "used_in_simulation" -value "0" -objects $file_obj
+
+
+# Set 'sources_1' fileset file properties for local files
+set file "src/cpuclk.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
+set_property -name "used_in_simulation" -value "0" -objects $file_obj
+
+set file "src/display_clock.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "is_enabled" -value "0" -objects $file_obj
+
+set file "src/mem.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
+set_property -name "used_in_simulation" -value "0" -objects $file_obj
+
+set file "src/stack.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
+set_property -name "used_in_simulation" -value "0" -objects $file_obj
+
+set file "src/stackcpu.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
+set_property -name "used_in_simulation" -value "0" -objects $file_obj
+
+set file "src/vgafb.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
+set_property -name "used_in_simulation" -value "0" -objects $file_obj
+
+set file "src/top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
+set_property -name "used_in_simulation" -value "0" -objects $file_obj
+
+set file "src/testbench.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "used_in" -value "" -objects $file_obj
+set_property -name "used_in_implementation" -value "0" -objects $file_obj
+set_property -name "used_in_simulation" -value "0" -objects $file_obj
+set_property -name "used_in_synthesis" -value "0" -objects $file_obj
+
+set file "arty-a7/rom.mem"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Memory File" -objects $file_obj
+
+set file "arty-a7/mig_dram_0/mig_a.prj"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "scoped_to_cells" -value "mig_dram_0" -objects $file_obj
+
+set file "arty-a7/mig_dram_0/mig_b.prj"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "scoped_to_cells" -value "mig_dram_0" -objects $file_obj
+
+set file "src/dram_bridge.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
+set_property -name "used_in_simulation" -value "0" -objects $file_obj
+
+set file "src/palette.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
+set_property -name "used_in_simulation" -value "0" -objects $file_obj
+
+set file "src/irqctrl.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
+set_property -name "used_in_simulation" -value "0" -objects $file_obj
+
+set file "src/fifo_testbench.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "used_in" -value "" -objects $file_obj
+set_property -name "used_in_implementation" -value "0" -objects $file_obj
+set_property -name "used_in_simulation" -value "0" -objects $file_obj
+set_property -name "used_in_synthesis" -value "0" -objects $file_obj
+
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Add local files from the original project (-no_copy_sources specified)
+set files [list \
+ [file normalize "${orig_proj_dir}/mig_dram_0/mig_dram_0.xci" ]\
+]
+set added_files [add_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file "arty-a7/mig_dram_0/mig_dram_0.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
+set_property -name "used_in_simulation" -value "0" -objects $file_obj
+
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize ${origin_dir}/arty-a7/Arty-A7-35-Master.xdc]"
+set file_added [add_files -norecurse -fileset $obj [list $file]]
+set file "$origin_dir/arty-a7/Arty-A7-35-Master.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_constrs_file" -value "$orig_proj_dir/Arty-A7-35-Master.xdc" -objects $obj
+set_property -name "target_ucf" -value "$orig_proj_dir/Arty-A7-35-Master.xdc" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+# Add local files from the original project (-no_copy_sources specified)
+set files [list \
+ [file normalize "${origin_dir}/src/uart_tb.v" ]\
+ [file normalize "${orig_proj_dir}/testbench_behav1.wcfg" ]\
+]
+set added_files [add_files -fileset sim_1 $files]
+
+# Set 'sim_1' fileset file properties for remote files
+# None
+
+# Set 'sim_1' fileset file properties for local files
+set file [file normalize "${origin_dir}/src/uart_tb.v"]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "used_in" -value "" -objects $file_obj
+set_property -name "used_in_implementation" -value "0" -objects $file_obj
+set_property -name "used_in_simulation" -value "0" -objects $file_obj
+set_property -name "used_in_synthesis" -value "0" -objects $file_obj
+
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
+set_property -name "nl.mode" -value "funcsim" -objects $obj
+set_property -name "top" -value "testbench" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
+
+# Create 'sim_fifo' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_fifo] ""]} {
+  create_fileset -simset sim_fifo
+}
+
+# Set 'sim_fifo' fileset object
+set obj [get_filesets sim_fifo]
+# Add local files from the original project (-no_copy_sources specified)
+set files [list \
+ [file normalize "${origin_dir}/src/fifo.v" ]\
+ [file normalize "${origin_dir}/src/fifo_testbench.v" ]\
+]
+set added_files [add_files -fileset sim_fifo $files]
+
+# Set 'sim_fifo' fileset file properties for remote files
+# None
+
+# Set 'sim_fifo' fileset file properties for local files
+# None
+
+# Set 'sim_fifo' fileset properties
+set obj [get_filesets sim_fifo]
+set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
+set_property -name "top" -value "fifo_testbench" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Create 'sim_sdspi' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_sdspi] ""]} {
+  create_fileset -simset sim_sdspi
+}
+
+# Set 'sim_sdspi' fileset object
+set obj [get_filesets sim_sdspi]
+# Add local files from the original project (-no_copy_sources specified)
+set files [list \
+ [file normalize "${orig_proj_dir}/sdspi_testbench_behav.wcfg" ]\
+]
+set added_files [add_files -fileset sim_sdspi $files]
+
+# Set 'sim_sdspi' fileset file properties for remote files
+# None
+
+# Set 'sim_sdspi' fileset file properties for local files
+# None
+
+# Set 'sim_sdspi' fileset properties
+set obj [get_filesets sim_sdspi]
+set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
+set_property -name "sim_mode" -value "post-synthesis" -objects $obj
+set_property -name "top" -value "sdspi_testbench" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "xsim.simulate.runtime" -value "10ms" -objects $obj
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7a35ticsg324-1L -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2020" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "needs_refresh" -value "1" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7a35ticsg324-1L -flow {Vivado Implementation 2020} -strategy "Performance_RefinePlacement" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Performance_RefinePlacement" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2020" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "needs_refresh" -value "1" -objects $obj
+set_property -name "strategy" -value "Performance_RefinePlacement" -objects $obj
+set_property -name "steps.place_design.args.directive" -value "ExtraPostPlacementOpt" -objects $obj
+set_property -name "steps.phys_opt_design.args.directive" -value "Explore" -objects $obj
+set_property -name "steps.route_design.args.directive" -value "Explore" -objects $obj
+set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1
--- a/tridoracpu/tridoracpu.srcs/bram_tdp.v
+++ b/tridoracpu/tridoracpu.srcs/bram_tdp.v
--- a/tridoracpu/tridoracpu.srcs/cpuclk.v
+++ b/tridoracpu/tridoracpu.srcs/cpuclk.v
--- a/tridoracpu/tridoracpu.srcs/display_clock.v
+++ b/tridoracpu/tridoracpu.srcs/display_clock.v
--- a/tridoracpu/tridoracpu.srcs/dram_bridge.v
+++ b/tridoracpu/tridoracpu.srcs/dram_bridge.v
--- a/tridoracpu/tridoracpu.srcs/fifo.v
+++ b/tridoracpu/tridoracpu.srcs/fifo.v
--- a/tridoracpu/tridoracpu.srcs/fifo_testbench.v
+++ b/tridoracpu/tridoracpu.srcs/fifo_testbench.v
--- a/tridoracpu/tridoracpu.srcs/irqctrl.v
+++ b/tridoracpu/tridoracpu.srcs/irqctrl.v
--- a/tridoracpu/tridoracpu.srcs/mem.v
+++ b/tridoracpu/tridoracpu.srcs/mem.v
--- a/tridoracpu/tridoracpu.srcs/palette.v
+++ b/tridoracpu/tridoracpu.srcs/palette.v
--- a/tridoracpu/tridoracpu.srcs/sdspi.v
+++ b/tridoracpu/tridoracpu.srcs/sdspi.v
--- a/tridoracpu/tridoracpu.srcs/sdspi_testbench.v
+++ b/tridoracpu/tridoracpu.srcs/sdspi_testbench.v
--- a/tridoracpu/tridoracpu.srcs/stack.v
+++ b/tridoracpu/tridoracpu.srcs/stack.v
--- a/tridoracpu/tridoracpu.srcs/stackcpu.v
+++ b/tridoracpu/tridoracpu.srcs/stackcpu.v
--- a/tridoracpu/tridoracpu.srcs/testbench.v
+++ b/tridoracpu/tridoracpu.srcs/testbench.v
--- a/tridoracpu/tridoracpu.srcs/top.v
+++ b/tridoracpu/tridoracpu.srcs/top.v
--- a/tridoracpu/tridoracpu.srcs/uart.v
+++ b/tridoracpu/tridoracpu.srcs/uart.v
--- a/tridoracpu/tridoracpu.srcs/uart_tb.v
+++ b/tridoracpu/tridoracpu.srcs/uart_tb.v
--- a/tridoracpu/tridoracpu.srcs/vgafb.v
+++ b/tridoracpu/tridoracpu.srcs/vgafb.v
--- a/tridoracpu/testbench_behav.wcfg
+++ b/tridoracpu/testbench_behav.wcfg
@ -1,272 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<wave_config>
-   <wave_state>
-   </wave_state>
-   <db_ref_list>
-      <db_ref path="testbench_behav.wdb" id="1">
-         <top_modules>
-            <top_module name="glbl" />
-            <top_module name="testbench" />
-         </top_modules>
-      </db_ref>
-   </db_ref_list>
-   <zoom_setting>
-      <ZoomStartTime time="0fs"></ZoomStartTime>
-      <ZoomEndTime time="516271fs"></ZoomEndTime>
-      <Cursor1Time time="48444fs"></Cursor1Time>
-   </zoom_setting>
-   <column_width_setting>
-      <NameColumnWidth column_width="240"></NameColumnWidth>
-      <ValueColumnWidth column_width="90"></ValueColumnWidth>
-   </column_width_setting>
-   <WVObjectSize size="39" />
-   <wvobject fp_name="/testbench/uut/seq_state" type="array">
-      <obj_property name="ElementShortName">seq_state[1:0]</obj_property>
-      <obj_property name="ObjectShortName">seq_state[1:0]</obj_property>
-      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/PC" type="array">
-      <obj_property name="ElementShortName">PC[15:0]</obj_property>
-      <obj_property name="ObjectShortName">PC[15:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="CustomSignalColor">#D2691E</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/nPC" type="array">
-      <obj_property name="ElementShortName">nPC[15:0]</obj_property>
-      <obj_property name="ObjectShortName">nPC[15:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="CustomSignalColor">#D2691E</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/ins" type="array">
-      <obj_property name="ElementShortName">ins[15:0]</obj_property>
-      <obj_property name="ObjectShortName">ins[15:0]</obj_property>
-      <obj_property name="CustomSignalColor">#D2691E</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/operand" type="array">
-      <obj_property name="ElementShortName">operand[15:0]</obj_property>
-      <obj_property name="ObjectShortName">operand[15:0]</obj_property>
-      <obj_property name="CustomSignalColor">#D2691E</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/ins_branch" type="logic">
-      <obj_property name="ElementShortName">ins_branch</obj_property>
-      <obj_property name="ObjectShortName">ins_branch</obj_property>
-      <obj_property name="CustomSignalColor">#D2691E</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/ins_cbranch" type="logic">
-      <obj_property name="ElementShortName">ins_cbranch</obj_property>
-      <obj_property name="ObjectShortName">ins_cbranch</obj_property>
-      <obj_property name="CustomSignalColor">#D2691E</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/ins_load" type="logic">
-      <obj_property name="ElementShortName">ins_load</obj_property>
-      <obj_property name="ObjectShortName">ins_load</obj_property>
-      <obj_property name="CustomSignalColor">#D2691E</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/ins_loadc" type="logic">
-      <obj_property name="ElementShortName">ins_loadc</obj_property>
-      <obj_property name="ObjectShortName">ins_loadc</obj_property>
-      <obj_property name="CustomSignalColor">#D2691E</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/ins_loadi" type="logic">
-      <obj_property name="ElementShortName">ins_loadi</obj_property>
-      <obj_property name="ObjectShortName">ins_loadi</obj_property>
-      <obj_property name="CustomSignalColor">#D2691E</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/ins_loadim" type="logic">
-      <obj_property name="ElementShortName">ins_loadim</obj_property>
-      <obj_property name="ObjectShortName">ins_loadim</obj_property>
-      <obj_property name="CustomSignalColor">#D2691E</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/ins_store" type="logic">
-      <obj_property name="ElementShortName">ins_store</obj_property>
-      <obj_property name="ObjectShortName">ins_store</obj_property>
-      <obj_property name="CustomSignalColor">#A52A2A</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/ins_aluop" type="logic">
-      <obj_property name="ElementShortName">ins_aluop</obj_property>
-      <obj_property name="ObjectShortName">ins_aluop</obj_property>
-      <obj_property name="CustomSignalColor">#D2691E</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/aluop" type="array">
-      <obj_property name="ElementShortName">aluop[3:0]</obj_property>
-      <obj_property name="ObjectShortName">aluop[3:0]</obj_property>
-      <obj_property name="CustomSignalColor">#FFD700</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-      <obj_property name="Radix">BINARYRADIX</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/aluop_sd" type="array">
-      <obj_property name="ElementShortName">aluop_sd[1:0]</obj_property>
-      <obj_property name="ObjectShortName">aluop_sd[1:0]</obj_property>
-      <obj_property name="CustomSignalColor">#FFD700</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-      <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/aluop_x2y" type="logic">
-      <obj_property name="ElementShortName">aluop_x2y</obj_property>
-      <obj_property name="ObjectShortName">aluop_x2y</obj_property>
-      <obj_property name="CustomSignalColor">#FFD700</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/mem_addr" type="array">
-      <obj_property name="ElementShortName">mem_addr[15:0]</obj_property>
-      <obj_property name="ObjectShortName">mem_addr[15:0]</obj_property>
-      <obj_property name="CustomSignalColor">#DCDCDC</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/mem_read_enable" type="logic">
-      <obj_property name="ElementShortName">mem_read_enable</obj_property>
-      <obj_property name="ObjectShortName">mem_read_enable</obj_property>
-      <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/mem_read_data" type="array">
-      <obj_property name="ElementShortName">mem_read_data[15:0]</obj_property>
-      <obj_property name="ObjectShortName">mem_read_data[15:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/mem_write_enable" type="logic">
-      <obj_property name="ElementShortName">mem_write_enable</obj_property>
-      <obj_property name="ObjectShortName">mem_write_enable</obj_property>
-      <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/mem_write_data" type="array">
-      <obj_property name="ElementShortName">mem_write_data[15:0]</obj_property>
-      <obj_property name="ObjectShortName">mem_write_data[15:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/X" type="array">
-      <obj_property name="ElementShortName">X[15:0]</obj_property>
-      <obj_property name="ObjectShortName">X[15:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="CustomSignalColor">#FF0080</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/nX" type="array">
-      <obj_property name="ElementShortName">nX[15:0]</obj_property>
-      <obj_property name="ObjectShortName">nX[15:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="CustomSignalColor">#FF0080</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/Y" type="array">
-      <obj_property name="ElementShortName">Y[15:0]</obj_property>
-      <obj_property name="ObjectShortName">Y[15:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="CustomSignalColor">#FF0080</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/FP" type="array">
-      <obj_property name="ElementShortName">FP[15:0]</obj_property>
-      <obj_property name="ObjectShortName">FP[15:0]</obj_property>
-      <obj_property name="CustomSignalColor">#DCDCDC</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/BP" type="array">
-      <obj_property name="ElementShortName">BP[15:0]</obj_property>
-      <obj_property name="ObjectShortName">BP[15:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="CustomSignalColor">#DCDCDC</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/RP" type="array">
-      <obj_property name="ElementShortName">RP[15:0]</obj_property>
-      <obj_property name="ObjectShortName">RP[15:0]</obj_property>
-      <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/nRP" type="array">
-      <obj_property name="ElementShortName">nRP[15:0]</obj_property>
-      <obj_property name="ObjectShortName">nRP[15:0]</obj_property>
-      <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/ESP" type="array">
-      <obj_property name="ElementShortName">ESP[5:0]</obj_property>
-      <obj_property name="ObjectShortName">ESP[5:0]</obj_property>
-      <obj_property name="CustomSignalColor">#008080</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/nESP" type="array">
-      <obj_property name="ElementShortName">nESP[5:0]</obj_property>
-      <obj_property name="ObjectShortName">nESP[5:0]</obj_property>
-      <obj_property name="CustomSignalColor">#008080</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/stack_write" type="logic">
-      <obj_property name="ElementShortName">stack_write</obj_property>
-      <obj_property name="ObjectShortName">stack_write</obj_property>
-      <obj_property name="CustomSignalColor">#008080</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/estack/stack[0]" type="array">
-      <obj_property name="ElementShortName">[0][15:0]</obj_property>
-      <obj_property name="ObjectShortName">[0][15:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/estack/stack[1]" type="array">
-      <obj_property name="ElementShortName">[1][15:0]</obj_property>
-      <obj_property name="ObjectShortName">[1][15:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/estack/stack[2]" type="array">
-      <obj_property name="ElementShortName">[2][15:0]</obj_property>
-      <obj_property name="ObjectShortName">[2][15:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/estack/stack[3]" type="array">
-      <obj_property name="ElementShortName">[3][15:0]</obj_property>
-      <obj_property name="ObjectShortName">[3][15:0]</obj_property>
-      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/estack/stack[4]" type="array">
-      <obj_property name="ElementShortName">[4][15:0]</obj_property>
-      <obj_property name="ObjectShortName">[4][15:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/estack/stack[5]" type="array">
-      <obj_property name="ElementShortName">[5][15:0]</obj_property>
-      <obj_property name="ObjectShortName">[5][15:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/estack/stack[6]" type="array">
-      <obj_property name="ElementShortName">[6][15:0]</obj_property>
-      <obj_property name="ObjectShortName">[6][15:0]</obj_property>
-      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-   <wvobject fp_name="/testbench/uut/estack/stack[7]" type="array">
-      <obj_property name="ElementShortName">[7][15:0]</obj_property>
-      <obj_property name="ObjectShortName">[7][15:0]</obj_property>
-      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
-</wave_config>
--- a/tridoracpu/tridoracpu.srcs/sfifo.v
+++ b/tridoracpu/tridoracpu.srcs/sfifo.v
@ -1,84 +0,0 @@
-`timescale 1ns / 1ps
-
-// a simple fifo
-module fifo #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 4)(
-    input wire clk,
-    input wire reset,
-    input wire wr_en,
-    input wire rd_en,
-    input wire [DATA_WIDTH-1:0] wr_data,
-    output wire [DATA_WIDTH-1:0] rd_data,
-    output wire wr_full,
-    output wire rd_empty
-    );
-
-    reg [DATA_WIDTH-1:0] mem [0:ADDR_WIDTH-1];
-    reg [ADDR_WIDTH:0]  head_x = 0;  // head and tail have one extra bit 
-    reg [ADDR_WIDTH:0]  tail_x = 0;  // for detecting overflows
-    wire [ADDR_WIDTH-1:0] head = head_x[ADDR_WIDTH-1:0];
-    wire [ADDR_WIDTH-1:0] tail = tail_x[ADDR_WIDTH-1:0];
-    
-    assign rd_data = mem[tail];
-    // the fifo is full when head and tail pointer are the same
-    // and the extra bits differ (a wraparound occured)
-    assign wr_full = (head == tail) && (head_x[ADDR_WIDTH] != tail_x[ADDR_WIDTH]);
-    // the fifo is empty when head and tail pointer are the same
-    // and the extra bits are the same (no wraparound)
-    assign rd_empty = (head == tail) && (head_x[ADDR_WIDTH] == tail_x[ADDR_WIDTH]);
-  
-    // Writing to FIFO
-    always @(posedge clk) begin
-        if (wr_en)
-        begin
-            mem[head[ADDR_WIDTH-1:0]] <= wr_data;
-            // move head, possible wraparound
-            head_x <= head_x + 1'b1;
-        end
-    end
-
-    // Reading from FIFO
-    always @(posedge clk)
-    begin
-        if (rd_en)
-        begin
-            // rd_data always has current tail data
-            // move tail, possible wraparound
-            tail <= tail + 1'b1;
-        end
-    end
-
-    // Calculating full/empty flags, referenced from zipcpu.com
-    wire	[c_DEPTH:0]	dblnext, nxtread;
-    assign	dblnext = wraddr + 2;
-    assign	nxtread = rdaddr + 1'b1;
-
-    always @(posedge i_Clock, negedge i_Reset)
-    
-        // Reset case
-        if (!i_Reset)
-        begin
-            // Reset output flags
-            fifo_full <= 1'b0;
-            fifo_empty <= 1'b1;
-            
-        end else casez({ i_Write_En, i_Read_En, !fifo_full, !fifo_empty })
-        4'b01?1: begin	// A successful read
-            fifo_full  <= 1'b0;
-            fifo_empty <= (nxtread == wraddr);
-        end
-        4'b101?: begin	// A successful write
-            fifo_full <= (dblnext == rdaddr);
-            fifo_empty <= 1'b0;
-        end
-        4'b11?0: begin	// Successful write, failed read
-            fifo_full  <= 1'b0;
-            fifo_empty <= 1'b0;
-        end
-        4'b11?1: begin	// Successful read and write
-            fifo_full  <= fifo_full;
-            fifo_empty <= 1'b0;
-        end
-        default: begin end
-        endcase
-    
-endmodule
--- a/tridoracpu/tridoracpu.xpr
+++ b/tridoracpu/tridoracpu.xpr
@ -1,417 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
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-<!--                                                         -->
-<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
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