diff --git a/.gitignore b/.gitignore
index 930fb01..b7537cf 100644
--- a/.gitignore
+++ b/.gitignore
@@ -33,7 +33,6 @@ pcomp/sdis
 tridoraemu/tridoraemu
 **/tridoracpu.cache/
 **/tridoracpu.hw/
-**/tridoracpu.gen/
 **/tridoracpu.ip_user_files/
 **/tridoracpu.runs/
 *.log
diff --git a/examples/benchmarks.results.text b/examples/benchmarks.results.text
index 5ae8a13..23da7c0 100644
--- a/examples/benchmarks.results.text
+++ b/examples/benchmarks.results.text
@@ -91,3 +91,4 @@ Running benchmarks.prog
                  array copy 128k 1K 00:00:48
                           exp() 10K 00:00:32
                           cos() 10K 00:00:06
+
diff --git a/lib/corelib.s b/lib/corelib.s
index 6970971..57f35a8 100644
--- a/lib/corelib.s
+++ b/lib/corelib.s
@@ -588,19 +588,13 @@ DIVU_END:
 
 ; wait approx. 1 millisecond
 ;
-; the ROM at address 4
-; contains the cpu clock freq in KHz
-	.EQU CLK_KHZ_ADDR 4
+; 83.333 MHz Clock, three instructions a 4 cycles
+; 83333 / 12 = 6944.4166
+; works only if executed without wait states (i.e.
+; from BRAM/SRAM)
 WAIT1MSEC:
-	LOADC CLK_KHZ_ADDR
-	LOADI
-	; divide by 16
-	SHR
-	SHR
-	SHR
-	SHR
+	LOADCP 6944
 WAIT1LOOP:
-	INC 0 ; NOP to make the loop 16 cycles long
 	DEC 1
 	DUP
 	CBRANCH.NZ WAIT1LOOP
diff --git a/lib/rommon.s b/lib/rommon.s
index a1034c5..a967e4b 100644
--- a/lib/rommon.s
+++ b/lib/rommon.s
@@ -7,16 +7,8 @@
 	.EQU UART_REG 2048
 	.EQU MON_ADDR 64512
 
-	.EQU CLK_KHZ 76923
-
 	BRANCH 2	; the very first instruction is not
 			; executed correctly
-	BRANCH MON_START ; branch over constant
-
-CLK_KHZ_ADDR:
-	.WORD CLK_KHZ  ; to calibrate the delay loop
-
-MON_START:
 	LOADCP 65020 ; initialise FP and RP registers
 	STOREREG FP
 	LOADCP 65024
@@ -790,17 +782,13 @@ COPY_BLK1:
 
 ; wait approx. 1 millisecond
 ;
+; 83.333 MHz Clock, three instructions a 4 cycles
+; 83333 / 12 = 6944.4166
+; works only if executed without wait states (i.e.
+; from BRAM/SRAM)
 WAIT1MSEC:
-	; get clock freq in khz
-	LOADC CLK_KHZ_ADDR
-	LOADI
-	; divide by 16
-	SHR
-	SHR
-	SHR
-	SHR
+	LOADCP 6944
 WAIT1LOOP:
-	INC 0	; NOP to make loop 16 cycles long
 	DEC 1
 	DUP
 	CBRANCH.NZ WAIT1LOOP
@@ -810,7 +798,7 @@ WAIT1LOOP:
 %include "sdcardboot.s"
 	.CPOOL
 MESSAGE:
-	.BYTE 13,10,"ROM Monitor v3.1.0", 13, 10,
+	.BYTE 13,10,"ROM Monitor v3.0.3", 13, 10,
 	      "Set A)ddress   D)eposit   eX)amine   L)oad   G)o  B)oot",13,10,0
 PROMPT2:
 	.BYTE "]> ",0
diff --git a/tridoracpu/tridoracpu.srcs/Arty-A7-35-Master.xdc b/tridoracpu/tridoracpu.srcs/Arty-A7-35-Master.xdc
index 7c62767..c618478 100644
--- a/tridoracpu/tridoracpu.srcs/Arty-A7-35-Master.xdc
+++ b/tridoracpu/tridoracpu.srcs/Arty-A7-35-Master.xdc
@@ -216,5 +216,3 @@ set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports rst]
 #set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
 
 set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
-
-set_max_delay -from [get_pins vgafb0/display_timings_inst/o_vblank_reg/C] -to [get_pins vgafb0/vblank_xfer_reg/D] 3.000
diff --git a/tridoracpu/tridoracpu.srcs/cpuclk.v b/tridoracpu/tridoracpu.srcs/cpuclk.v
index a214cc4..613d85e 100644
--- a/tridoracpu/tridoracpu.srcs/cpuclk.v
+++ b/tridoracpu/tridoracpu.srcs/cpuclk.v
@@ -17,9 +17,7 @@ module cpu_clkgen(
         .CLKFBOUT_PHASE(0.0),       // Phase offset in degrees of CLKFB (-360.000-360.000).
         .CLKIN1_PERIOD(10.0),       // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
         // CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
-        // CPU Clock: 12.0 = 83.33MHz CPU Clock, 333.33MHz Memory Clock
-        // 13.0 = 76.92MHz CPU Clock, 307.69MHz Memory Clock
-        .CLKOUT0_DIVIDE_F(13.0),    // Divide amount for CLKOUT0 (1.000-128.000).
+        .CLKOUT0_DIVIDE_F(12.0),    // Divide amount for CLKOUT0 (1.000-128.000).
         .CLKOUT1_DIVIDE(5),
         .CLKOUT2_DIVIDE(40),        // 40 = 25MHz pixel clock (should be 25.175MHz per spec) for 640x480
         //.CLKOUT2_DIVIDE(25),        // 25 = 40MHz pixel clock for 800x600
diff --git a/tridoracpu/tridoracpu.srcs/dram_bridge.v b/tridoracpu/tridoracpu.srcs/dram_bridge.v
index c3f948a..102a8cf 100644
--- a/tridoracpu/tridoracpu.srcs/dram_bridge.v
+++ b/tridoracpu/tridoracpu.srcs/dram_bridge.v
@@ -8,7 +8,6 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
     input wire [WIDTH-1:0]      mem_write_data,
     input wire                  mem_read_enable,
     input wire                  mem_write_enable,
-    input wire                  mem_read_ins,
     output wire                 mem_wait,
 
     input wire                  rst_n,
@@ -106,38 +105,33 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
        .sys_rst                        (rst_n)
     );
 
-    (*KEEP*) reg [DRAM_DATA_WIDTH-1:0] 	ins_cache;
-    (*KEEP*) reg [DRAM_ADDR_WIDTH-1:4]  cached_addr;
-    (*KEEP*) wire 		      	        cache_hit = mem_read_enable && mem_read_ins && (cached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4]);
+//    reg [DRAM_DATA_WIDTH-1:0] 	read_cache;
+//    reg [ADDR_WIDTH-1:0]      	cached_addr;
+//    wire 		      	cache_hit = cached_addr == mem_addr;
+//    wire [DRAM_DATA_WIDTH-1:0]  read_data_wrapper = cache_hit ? read_cache : app_rd_data;
 
     reg [WIDTH-1:0] read_buf;
     reg read_inprogress = 0;
-    wire dram_read_enable = mem_read_enable && !cache_hit;
 
     assign app_rd_data_end = 1'b1;
+    //assign app_wdf_mask = 16'b1111111111111100;
 
     // addresses on the memory interface are aligned to 16 bytes
     // and 28 bits wide (=256MB)
     assign app_addr = { mem_addr[DRAM_ADDR_WIDTH:4], 4'b0000 };
+    //assign app_addr = { 28'b0 };
  
     // select a word from the 128 bits transferred by the dram controller
     // according to the lower bits of the address (ignoring bits 1:0)
+    wire [WIDTH-1:0] read_word;
     wire [1:0] word_sel = mem_addr[3:2];
 
-    wire [WIDTH-1:0] read_word =
-                        word_sel == 3'b11 ? app_rd_data[31:0]  :
+    assign read_word =  word_sel == 3'b11 ? app_rd_data[31:0]  :
                         word_sel == 3'b10 ? app_rd_data[63:32] :
                         word_sel == 3'b01 ? app_rd_data[95:64] :
                                             app_rd_data[127:96];
 
-    wire [WIDTH-1:0] read_cached_word =
-                        word_sel == 3'b11 ? ins_cache[31:0]  :
-                        word_sel == 3'b10 ? ins_cache[63:32] :
-                        word_sel == 3'b01 ? ins_cache[95:64] :
-                                            ins_cache[127:96];
-
-    (*KEEP*) assign mem_read_data = cache_hit ? read_cached_word :
-                            app_rd_data_valid ? read_word : read_buf;
+    assign mem_read_data = app_rd_data_valid ? read_word : read_buf;
 
     // set the write mask according to the lower bits of the address
     // (ignoring bit 0)
@@ -151,34 +145,21 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
     assign app_wdf_end =  mem_write_enable & write_ready;
     assign app_wdf_data = { {4{mem_write_data}} };
 
-    assign mem_wait =   (dram_read_enable & ~read_inprogress) |
+    assign mem_wait =   (mem_read_enable & ~read_inprogress) |
                         (mem_write_enable & (~app_wdf_rdy | ~app_rdy)) |
                         (read_inprogress & ~app_rd_data_valid);
 
-    assign app_en = (dram_read_enable & ~read_inprogress) |
+    assign app_en = (mem_read_enable & ~read_inprogress) |
             (mem_write_enable & write_ready);
-    assign app_cmd = dram_read_enable ? CMD_READ : CMD_WRITE;
-
+    assign app_cmd = mem_read_enable ? CMD_READ : CMD_WRITE;
 
     always @(posedge dram_front_clk)
     begin
-        if(dram_read_enable && mem_read_ins && app_rd_data_valid)
-        begin
-            ins_cache <= app_rd_data;
-            cached_addr <= mem_addr[DRAM_ADDR_WIDTH-1:4];
-        end
-    end
-
-    always @(posedge dram_front_clk)
-    begin
-        if(dram_read_enable & ~read_inprogress & app_rdy)
+        if(mem_read_enable & ~read_inprogress & app_rdy)
             read_inprogress <= 1;
         if(read_inprogress & app_rd_data_valid)
             read_inprogress <= 0;
-        if(dram_read_enable & app_rd_data_valid)
+        if(mem_read_enable & app_rd_data_valid)
             read_buf <= mem_read_data;
-        else
-        if (mem_read_enable & cache_hit)
-            read_buf <= read_cached_word;
     end
 endmodule
diff --git a/tridoracpu/tridoracpu.srcs/mig_dram_0/mig_a.prj b/tridoracpu/tridoracpu.srcs/mig_dram_0/mig_a.prj
index 58ff963..b263a25 100644
--- a/tridoracpu/tridoracpu.srcs/mig_dram_0/mig_a.prj
+++ b/tridoracpu/tridoracpu.srcs/mig_dram_0/mig_a.prj
@@ -39,12 +39,12 @@
 
   <Controller number="0">
     <MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
-    <TimePeriod>3300</TimePeriod>
+    <TimePeriod>3000</TimePeriod>
     <VccAuxIO>1.8V</VccAuxIO>
     <PHYRatio>4:1</PHYRatio>
-    <InputClkFreq>75.757</InputClkFreq>
+    <InputClkFreq>83.333</InputClkFreq>
     <UIExtraClocks>0</UIExtraClocks>
-    <MMCM_VCO>606</MMCM_VCO>
+    <MMCM_VCO>666</MMCM_VCO>
     <MMCMClkOut0> 1.000</MMCMClkOut0>
     <MMCMClkOut1>1</MMCMClkOut1>
     <MMCMClkOut2>1</MMCMClkOut2>
diff --git a/tridoracpu/tridoracpu.srcs/mig_dram_0/mig_b.prj b/tridoracpu/tridoracpu.srcs/mig_dram_0/mig_b.prj
index 99d2e0c..b263a25 100644
--- a/tridoracpu/tridoracpu.srcs/mig_dram_0/mig_b.prj
+++ b/tridoracpu/tridoracpu.srcs/mig_dram_0/mig_b.prj
@@ -39,12 +39,12 @@
 
   <Controller number="0">
     <MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
-    <TimePeriod>3250</TimePeriod>
+    <TimePeriod>3000</TimePeriod>
     <VccAuxIO>1.8V</VccAuxIO>
     <PHYRatio>4:1</PHYRatio>
-    <InputClkFreq>76.923</InputClkFreq>
+    <InputClkFreq>83.333</InputClkFreq>
     <UIExtraClocks>0</UIExtraClocks>
-    <MMCM_VCO>615</MMCM_VCO>
+    <MMCM_VCO>666</MMCM_VCO>
     <MMCMClkOut0> 1.000</MMCMClkOut0>
     <MMCMClkOut1>1</MMCMClkOut1>
     <MMCMClkOut2>1</MMCMClkOut2>
diff --git a/tridoracpu/tridoracpu.srcs/sdspi.v b/tridoracpu/tridoracpu.srcs/sdspi.v
index 9f5c84d..7141288 100644
--- a/tridoracpu/tridoracpu.srcs/sdspi.v
+++ b/tridoracpu/tridoracpu.srcs/sdspi.v
@@ -107,7 +107,7 @@ module sdspi(
         tx_fifo_empty
     );
 
-    fifo #(.ADDR_WIDTH(10)) rx_fifo(clk, reset,
+    fifo #(.ADDR_WIDTH(8)) rx_fifo(clk, reset,
         rx_fifo_wr_en, rx_fifo_rd_en,
         rx_shifter, rx_fifo_out,
         rx_fifo_full,
diff --git a/tridoracpu/tridoracpu.srcs/stackcpu.v b/tridoracpu/tridoracpu.srcs/stackcpu.v
index 33b58ec..c65ae4e 100644
--- a/tridoracpu/tridoracpu.srcs/stackcpu.v
+++ b/tridoracpu/tridoracpu.srcs/stackcpu.v
@@ -11,14 +11,20 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
     output reg [ADDR_WIDTH-1:0] addr,
     input wire [WIDTH-1:0] data_in,
     output wire read_enable,
-    output wire read_ins,
     output wire [WIDTH-1:0] data_out,
     output wire write_enable,
     input wire mem_wait,
     
     output wire led1,
     output wire led2,
-    output wire led3
+    output wire led3,
+    
+    output wire [WIDTH-1:0] debug_out1,
+    output wire [WIDTH-1:0] debug_out2,
+    output wire [WIDTH-1:0] debug_out3,
+    output wire [WIDTH-1:0] debug_out4,
+    output wire [WIDTH-1:0] debug_out5,
+    output wire [WIDTH-1:0] debug_out6
     );
     
     localparam EVAL_STACK_INDEX_WIDTH = 6;
@@ -176,8 +182,6 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
     assign mem_read_enable  = (seq_state == FETCH) || (seq_state == EXEC && mem_read);
     assign mem_write_enable = (seq_state == MEM && mem_write);
     
-    assign read_ins = (seq_state == FETCH) || (seq_state == DECODE);
- 
     initial
     begin
         PC <= 0; nPC <= 0; seq_state <= MEM;
diff --git a/tridoracpu/tridoracpu.srcs/top.v b/tridoracpu/tridoracpu.srcs/top.v
index 00066fe..e79d611 100644
--- a/tridoracpu/tridoracpu.srcs/top.v
+++ b/tridoracpu/tridoracpu.srcs/top.v
@@ -3,8 +3,7 @@
 // or as clk_1hz for debugging
 
 `define clock cpuclk
-//`define clkfreq 83333333
-`define clkfreq 76923076
+`define clkfreq 83333333
 //`define clock clk
 //`define clkfreq 100000000
 //`define clock clk_1hz
@@ -68,11 +67,10 @@ module top(
     localparam ADDR_WIDTH = 32, WIDTH = 32,
             ROMADDR_WIDTH = 11, IOADDR_WIDTH = 11, IOADDR_SEL = 4;
     
-    (* KEEP *) wire [ADDR_WIDTH-1:0] mem_addr;
+    wire [ADDR_WIDTH-1:0] mem_addr;
     wire [WIDTH-1:0] mem_read_data;
     wire [WIDTH-1:0] mem_write_data;
     (* KEEP *) wire mem_wait;
-    assign led0 = mem_wait;
 
     (* KEEP *) wire mem_read_enable;
     (* KEEP *) wire mem_write_enable;
@@ -82,6 +80,14 @@ module top(
 
     wire irq;
 
+    // assign led0 = mem_wait;
+    
+    wire [WIDTH-1:0] debug_data1, debug_data2,
+        debug_data3, debug_data4,
+        debug_data5, debug_data6;
+
+    assign led0 = debug_data6[0];
+
     wire cpuclk, cpuclk_locked;
     wire dram_refclk200;
     wire pixclk;
@@ -91,11 +97,9 @@ module top(
     wire [ADDR_WIDTH-1:0] dram_addr;
     wire [WIDTH-1:0] dram_read_data, dram_write_data;
     wire dram_read_enable, dram_write_enable, dram_wait;
-    (* KEEP *) wire dram_read_ins;
 
     dram_bridge dram_bridge0 (dram_addr,
-        dram_read_data, dram_write_data, dram_read_enable, dram_write_enable,
-        dram_read_ins, dram_wait,
+        dram_read_data, dram_write_data, dram_read_enable, dram_write_enable, dram_wait,
         rst, cpuclk, dram_refclk200,
         ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr,
         ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n,
@@ -250,10 +254,15 @@ module top(
     stackcpu cpu0(.clk(`clock), .rst(rst), .irq(irq),
         .addr(mem_addr),
         .data_in(mem_read_data), .read_enable(mem_read_enable),
-        .read_ins(dram_read_ins),
         .data_out(mem_write_data), .write_enable(mem_write_enable),
         .mem_wait(mem_wait),
-        .led1(led1), .led2(led2), .led3(led3));
+        .led1(led1), .led2(led2), .led3(led3),
+        .debug_out1(debug_data1),
+        .debug_out2(debug_data2),
+        .debug_out3(debug_data3),
+        .debug_out4(debug_data4),
+        .debug_out5(debug_data5),
+        .debug_out6(debug_data6));
 
     // Interrupt Controller
     irqctrl irqctrl0(`clock, irq_in, irqc_cs, mem_write_enable,
diff --git a/tridoracpu/tridoracpu.srcs/vgafb.v b/tridoracpu/tridoracpu.srcs/vgafb.v
index 37c1376..4e8d668 100644
--- a/tridoracpu/tridoracpu.srcs/vgafb.v
+++ b/tridoracpu/tridoracpu.srcs/vgafb.v
@@ -62,11 +62,10 @@ module display_timings #(
     // o_scanline: high for one tick at the start of each visible scanline
     assign o_scanline = (o_sy >= VA_STA) && (o_sy <= VA_END) && (o_sx == H_STA);
 
-    // set vblank at end of frame, clear at start
     always @(posedge i_pix_clk)
     begin
-        if(o_sy == VA_END) o_vblank <= 1;
-        else if (o_sy == -1) o_vblank <= 0;
+        if(o_frame) o_vblank <= 1;
+        else if (o_de) o_vblank <= 0;
     end
 
     always @ (posedge i_pix_clk)
@@ -176,7 +175,6 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
     wire scanline;                  // scanline start
     wire vblank;                    // vertical blank
     reg  vblank_buf;                // vertical blank in cpu clock domain
-    reg  vblank_xfer;               // vertical blank clock domain crossing
 
     display_timings #(              // 640x480  800x600 1280x720 1920x1080
 `ifdef RES_1024_768
@@ -235,7 +233,7 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
 
     always @(posedge pix_clk) frame_d <= frame;
 
-    always @(posedge cpu_clk) { vblank_buf, vblank_xfer } <= { vblank_xfer, vblank };
+    always @(posedge cpu_clk) vblank_buf <= vblank;
 
     always @(posedge cpu_clk)
     begin
diff --git a/tridoracpu/tridoracpu.xpr b/tridoracpu/tridoracpu.xpr
index 05c7b30..a4c6545 100644
--- a/tridoracpu/tridoracpu.xpr
+++ b/tridoracpu/tridoracpu.xpr
@@ -1,10 +1,9 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2024.2.2 (64-bit)                              -->
-<!--                                                                         -->
-<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Product Version: Vivado v2020.1 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="68" Path="C:/Users/sebastian/develop/Tridora-NexysA7/Tridora-CPU/tridoracpu/tridoracpu.xpr">
+<Project Version="7" Minor="49" Path="./tridoracpu.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
     <Option Name="Id" Val="ab60beb5e7ec4efc9a7b17699b9c3b13"/>
@@ -13,48 +12,29 @@
     <Option Name="CompiledLibDirXSim" Val=""/>
     <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
     <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
     <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
     <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
     <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
     <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
     <Option Name="SimulatorInstallDirModelSim" Val=""/>
     <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirIES" Val=""/>
     <Option Name="SimulatorInstallDirXcelium" Val=""/>
     <Option Name="SimulatorInstallDirVCS" Val=""/>
     <Option Name="SimulatorInstallDirRiviera" Val=""/>
     <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
-    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
-    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
-    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
-    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
-    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2024.2"/>
-    <Option Name="SimulatorVersionModelSim" Val="2024.1"/>
-    <Option Name="SimulatorVersionQuesta" Val="2024.1"/>
-    <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
-    <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2024.04"/>
-    <Option Name="SimulatorVersionActiveHdl" Val="15.0"/>
-    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
-    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
-    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
-    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
-    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
-    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
-    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
-    <Option Name="BoardPart" Val=""/>
+    <Option Name="BoardPart" Val="digilentinc.com:arty-a7-35:part0:1.0"/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../AppData/Roaming/Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store"/>
     <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
     <Option Name="ActiveSimSet" Val="sim_sdspi"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
     <Option Name="ProjectType" Val="Default"/>
     <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
-    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPDefaultOutputPath" Val="$PSRCDIR/sources_1"/>
     <Option Name="IPCachePermission" Val="read"/>
     <Option Name="IPCachePermission" Val="write"/>
     <Option Name="EnableCoreContainer" Val="FALSE"/>
-    <Option Name="EnableResourceEstimation" Val="FALSE"/>
-    <Option Name="SimCompileState" Val="TRUE"/>
     <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
@@ -67,13 +47,13 @@
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="6"/>
-    <Option Name="WTModelSimExportSim" Val="6"/>
-    <Option Name="WTQuestaExportSim" Val="6"/>
+    <Option Name="WTXSimExportSim" Val="4"/>
+    <Option Name="WTModelSimExportSim" Val="4"/>
+    <Option Name="WTQuestaExportSim" Val="4"/>
     <Option Name="WTIesExportSim" Val="4"/>
-    <Option Name="WTVcsExportSim" Val="6"/>
-    <Option Name="WTRivieraExportSim" Val="6"/>
-    <Option Name="WTActivehdlExportSim" Val="6"/>
+    <Option Name="WTVcsExportSim" Val="4"/>
+    <Option Name="WTRivieraExportSim" Val="4"/>
+    <Option Name="WTActivehdlExportSim" Val="4"/>
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
     <Option Name="XSimRadix" Val="hex"/>
     <Option Name="XSimTimeUnit" Val="ns"/>
@@ -85,11 +65,9 @@
     <Option Name="SimTypes" Val="tlm_dpi"/>
     <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
     <Option Name="DcpsUptoDate" Val="TRUE"/>
-    <Option Name="UseInlineHdlIP" Val="TRUE"/>
-    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
   </Configuration>
-  <FileSets Version="1" Minor="32">
-    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR" RelGenDir="$PGENDIR/sources_1">
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR">
       <Filter Type="Srcs"/>
       <File Path="$PSRCDIR/cpuclk.v">
         <FileInfo>
@@ -210,7 +188,7 @@
         <Option Name="TopModule" Val="top"/>
       </Config>
     </FileSet>
-    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR" RelGenDir="$PGENDIR/constrs_1">
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR">
       <Filter Type="Constrs"/>
       <File Path="$PSRCDIR/Arty-A7-35-Master.xdc">
         <FileInfo>
@@ -223,7 +201,7 @@
         <Option Name="ConstrsType" Val="XDC"/>
       </Config>
     </FileSet>
-    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR" RelGenDir="$PGENDIR/sim_1">
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR">
       <Filter Type="Srcs"/>
       <File Path="$PSRCDIR/uart_tb.v"/>
       <File Path="$PPRDIR/testbench_behav1.wcfg">
@@ -246,19 +224,28 @@
         <Option Name="SrcSet" Val="sources_1"/>
         <Option Name="XSimWcfgFile" Val="$PPRDIR/testbench_behav.wcfg"/>
         <Option Name="XSimWcfgFile" Val="$PPRDIR/testbench_behav1.wcfg"/>
-        <Option Name="CosimPdi" Val=""/>
-        <Option Name="CosimPlatform" Val=""/>
-        <Option Name="CosimElf" Val=""/>
         <Option Name="NLNetlistMode" Val="funcsim"/>
       </Config>
     </FileSet>
-    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
       <Filter Type="Utils"/>
       <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
-    <FileSet Name="sim_fifo" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_fifo" RelGenDir="$PGENDIR/sim_fifo">
+    <FileSet Name="mig_dram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/mig_dram_0">
+      <File Path="$PSRCDIR/mig_dram_0/mig_dram_0.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="mig_dram_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_fifo" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_fifo">
       <Filter Type="Srcs"/>
       <File Path="$PSRCDIR/fifo.v">
         <FileInfo>
@@ -285,12 +272,9 @@
         <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
         <Option Name="PamPseudoTop" Val="pseudo_tb"/>
         <Option Name="SrcSet" Val="sources_1"/>
-        <Option Name="CosimPdi" Val=""/>
-        <Option Name="CosimPlatform" Val=""/>
-        <Option Name="CosimElf" Val=""/>
       </Config>
     </FileSet>
-    <FileSet Name="sim_sdspi" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_sdspi" RelGenDir="$PGENDIR/sim_sdspi">
+    <FileSet Name="sim_sdspi" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_sdspi">
       <Filter Type="Srcs"/>
       <File Path="$PPRDIR/sdspi_testbench_behav.wcfg">
         <FileInfo>
@@ -311,24 +295,9 @@
         <Option Name="PamPseudoTop" Val="pseudo_tb"/>
         <Option Name="SrcSet" Val="sources_1"/>
         <Option Name="XSimWcfgFile" Val="$PPRDIR/sdspi_testbench_behav.wcfg"/>
-        <Option Name="CosimPdi" Val=""/>
-        <Option Name="CosimPlatform" Val=""/>
-        <Option Name="CosimElf" Val=""/>
         <Option Name="xsim.simulate.runtime" Val="10ms"/>
       </Config>
     </FileSet>
-    <FileSet Name="mig_dram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/mig_dram_0" RelGenDir="$PGENDIR/mig_dram_0">
-      <File Path="$PSRCDIR/mig_dram_0/mig_dram_0.xci">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-        </FileInfo>
-      </File>
-      <Config>
-        <Option Name="TopModule" Val="mig_dram_0"/>
-        <Option Name="UseBlackboxStub" Val="1"/>
-      </Config>
-    </FileSet>
   </FileSets>
   <Simulators>
     <Simulator Name="XSim">
@@ -348,8 +317,8 @@
       <Option Name="Description" Val="Active-HDL Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="22">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+  <Runs Version="1" Minor="11">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
         <Step Id="synth_design"/>
@@ -359,17 +328,17 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" ParallelReportGen="true">
+    <Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Increase placer effort in the post-placement optimization phase, and disable timing relaxation in the router." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Increase placer effort in the post-placement optimization phase, and disable timing relaxation in the router." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Performance_RefinePlacement" Flow="Vivado Implementation 2020"/>
         <Step Id="init_design"/>
@@ -395,9 +364,9 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" ParallelReportGen="true">
+    <Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -408,12 +377,14 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
   </Runs>
-  <Board/>
+  <Board>
+    <Jumpers/>
+  </Board>
   <DashboardSummary Version="1" Minor="0">
     <Dashboards>
       <Dashboard Name="default_dashboard">