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base: slederer:8c420dff752909b20669fc739c54f1cd00f25e67
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slederer:main
slederer:tdraudio-pcm
slederer:tdraudio
slederer:dcache
slederer:vga480
slederer:inscache
slederer:sasm-linker
slederer:October-2025-Update
slederer:April-2025-Update
..
compare: slederer:e08d610aef5ed9e5afb385d9e7b2679a9504e2da
Branches Tags
slederer:main
slederer:tdraudio-pcm
slederer:tdraudio
slederer:dcache
slederer:vga480
slederer:inscache
slederer:sasm-linker
slederer:October-2025-Update
slederer:April-2025-Update

No commits in common. "8c420dff752909b20669fc739c54f1cd00f25e67" and "e08d610aef5ed9e5afb385d9e7b2679a9504e2da" have entirely different histories.
8c420dff75 ... e08d610aef

7 changed files with 19 additions and 216 deletions
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1
pcomp/Makefile
View file

@ -31,7 +31,6 @@ nativeprogs: nativecomp
$(PCOMP) ../progs/partmgr.pas
$(PCOMP) ../progs/xfer.pas
$(PCOMP) ../progs/recover.pas
$(PCOMP) ../progs/changemem.pas
$(SASM) ../lib/rommon.s
$(SASM) -A ../lib/rommon.s ../lib/rom.mem

1
pcomp/make.bat
View file

@ -28,7 +28,6 @@ py pcomp.py ..\progs\dumpdir.pas
py pcomp.py ..\progs\partmgr.pas
py pcomp.py ..\progs\xfer.pas
py pcomp.py ..\progs\recover.pas
py pcomp.py ..\progs\changemem.pas
sasm ..\lib\rommon.s
sasm -A ..\lib\rommon.s ..\lib\rom.mem

2
pcomp/sasm.pas
View file

@ -1,7 +1,7 @@
(* Copyright 2021-2024 Sebastian Lederer. See the file LICENSE.md for details *)
{$MODE objfpc}
{$H600}
{$S32}
{$S4}
program sasm;
{$!}{$ifdef FPC}uses math,crt;{$endif}
{$R+}

173
progs/changemem.pas
View file

@ -1,173 +0,0 @@
program changemem;
const ProgramMagic = $00100AFE;
type ProgramHeader = record
magic:integer;
heapSize:integer;
stackSize:integer;
mainPtr:integer;
end;
var filename:string;
h:ProgramHeader;
procedure showHex(value:integer);
var i:integer;
digit:integer;
digits:array[1..8] of char;
ch:char;
begin
for i := 1 to 8 do
begin
digit := value and 15;
value := value shr 4;
if digit < 10 then
ch := chr(digit + ord('0'))
else
ch := chr(digit - 10 + ord('A'));
digits[i] := ch;
end;
for i := 8 downto 1 do
write(digits[i]);
end;
procedure showValue(labl:string; value:integer);
begin
write(labl:20, ' ');
write(value:8, ' (');
showHex(value);
writeln(')');
end;
procedure showHeader(var h:ProgramHeader);
begin
showValue('heap size', h.heapSize);
showValue('stack size', h.stackSize);
showValue('main entry point', h.mainPtr);
end;
procedure readHeader(var filename:string;var h:ProgramHeader);
var f:file;
begin
writeln('reading file ', filename);
open(f, filename, ModeReadOnly);
if IOResult(f) <> 0 then
begin
writeln('Error opening file: ', ErrorStr(IOResult(f)));
halt;
end
else
begin
read(f, h);
if IOResult(f) <> 0 then
begin
writeln('Error reading header: ', ErrorStr(IOResult(f)));
halt;
end;
close(f);
end;
end;
procedure writeHeader(var filename:string;var h:ProgramHeader);
var f:file;
begin
writeln('writing file ', filename);
open(f, filename, ModeModify);
if IOResult(f) <> 0 then
begin
writeln('Error opening file: ', ErrorStr(IOResult(f)));
halt;
end
else
begin
write(f, h);
if IOResult(f) <> 0 then
begin
writeln('Error writing header: ', ErrorStr(IOResult(f)));
halt;
end;
close(f);
end;
end;
procedure modifyHeader(var filename:string;var h:ProgramHeader);
var done:boolean;
ch:char;
changed:boolean;
function getNewValue(descr:string):integer;
var buf:string;
v,e:integer;
begin
getNewValue := 0;
write('New ',descr, ' size (decimal)> ');
readln(buf);
val(buf, v, e);
if(e > 0 ) or (v <= 0) then
writeln('invalid size')
else
getNewValue := v;
end;
procedure changeStackSize;
var v:integer;
begin
v := getNewValue('stack');
if v > 0 then
begin
h.stackSize := v;
changed := true;
end;
end;
procedure changeHeapSize;
var v:integer;
begin
v := getNewValue('heap');
if v > 0 then
begin
h.heapSize := v;
changed := true;
end;
end;
begin
changed := false; done := false;
while not done do
begin
writeln(filename, ' header:');
showHeader(h);
writeln('Change H)eap size Change S)tack size eX)it');
write('> ');
read(ch);
writeln;
case upcase(ch) of
'S': changeStackSize;
'H': changeHeapSize;
'X': done := true;
else
writeln('invalid command');
end;
end;
if changed then
writeHeader(filename, h);
end;
begin
if ParamCount > 0 then
filename := ParamStr(1)
else
begin
write('File name> ');
readln(filename);
end;
readHeader(filename, h);
if h.magic <> ProgramMagic then
writeln('invalid magic value ', h.magic)
else
modifyHeader(filename, h);
end.

27
tridoracpu/tridoracpu.srcs/vgafb.v
View file

@ -6,11 +6,8 @@
// Learn more at https://projectf.io
//128K video memory is not enough for 640x480x4
//`define RES_640_400
`define RES_640_400
//`define RES_1024_768
// RES_640_480 mode displays 400 lines with 640x480/60 video timings,
// adding blank lines at the bottom
`define RES_640_480
module display_timings #(
H_RES=640, // horizontal resolution (pixels)
@ -129,8 +126,6 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
localparam COLOR_WIDTH = 12;
localparam PALETTE_WIDTH = 4;
localparam signed PIC_LINES = 400; // visible picture lines
// Display Clocks
wire pix_clk = CLK; // pixel clock
wire clk_lock = 1; // clock locked?
@ -207,18 +202,6 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
.V_BP(35),
.H_POL(0),
.V_POL(1)
`endif
`ifdef RES_640_480
.H_RES(640), // 640 800 1280 1920
.V_RES(480), // 480 600 720 1080
.H_FP(16), // 16 40 110 88
.H_SYNC(96), // 96 128 40 44
.H_BP(48), // 48 88 220 148
.V_FP(10), // 10 1 5 4
.V_SYNC(2), // 2 4 5 5
.V_BP(33), // 33 23 20 36
.H_POL(0), // 0 1 1 1
.V_POL(0) // 0 1 1 1
`endif
)
display_timings_inst (
@ -234,8 +217,6 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
.o_sy(sy)
);
wire pic_enable = (sy >= 0) && (sy < PIC_LINES); // when to display pixels from VRAM
wire [7:0] red;
wire [7:0] green;
wire [7:0] blue;
@ -307,7 +288,7 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
// 12 bit RGB palette
assign VGA_HS = h_sync;
assign VGA_VS = v_sync;
assign VGA_R = (pic_enable && de) ? color_data[11:8] : 4'b0;
assign VGA_G = (pic_enable && de) ? color_data[7:4] : 4'b0;
assign VGA_B = (pic_enable && de) ? color_data[3:0] : 4'b0;
assign VGA_R = de ? color_data[11:8] : 4'b0;
assign VGA_G = de ? color_data[7:4] : 4'b0;
assign VGA_B = de ? color_data[3:0] : 4'b0;
endmodule

30
tridoracpu/tridoracpu.xpr
View file

@ -351,9 +351,7 @@
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -363,7 +361,9 @@
</Run>
<Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -371,25 +371,21 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Best predicted directive for place_design." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Increase placer effort in the post-placement optimization phase, and disable timing relaxation in the router." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Performance_Auto_1" Flow="Vivado Implementation 2024">
<Desc>Best predicted directive for place_design.</Desc>
</StratHandle>
<StratHandle Name="Performance_RefinePlacement" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design">
<Option Id="Directive">0</Option>
</Step>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design">
<Option Id="Directive">20</Option>
<Option Id="Directive">7</Option>
</Step>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design">
<Option Id="Directive">2</Option>
<Option Id="Directive">0</Option>
</Step>
<Step Id="route_design">
<Option Id="Directive">1</Option>
<Option Id="Directive">0</Option>
</Step>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream">
@ -397,13 +393,15 @@
</Step>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>

1
utils/tdrimg.py
View file

@ -536,7 +536,6 @@ def create_image_with_stuff(imgfile):
slotnr = putfile("../progs/editor.prog", None , f, part, partstart, slotnr)
slotnr = putfile("../progs/xfer.prog", None , f, part, partstart, slotnr)
slotnr = putfile("../progs/recover.prog", None , f, part, partstart, slotnr)
slotnr = putfile("../progs/changemem.prog", None , f, part, partstart, slotnr)
listdir(f, part)