added missing assembly files, extended .gitignore

lib/stdlib.pas

@@ -2337,7 +2337,7 @@ begin
 		if f.raw then
 			writechannel(f, aChar)
 		else
-		if (aChar <> #8) and (aChar <> #127) and (aChar <> #4) then
+		if (aChar <> #8) and (aChar <> #9) and (aChar <> #4) then
 		begin
 			writechannel(f,aChar);
 			if aChar = #13 then

pcomp/make.bat

@@ -1,14 +1,11 @@
 del *.s
-del ..\lib\*.lib
-del ..\lib\stdlib.s
-
 fpc -Mobjfpc -gl pcomp.pas
 fpc -gl sasm.pas
 fpc -gl lsymgen.pas
 
 sasm ..\lib\coreloader.s
 lsymgen ..\lib\coreloader.sym
-py pcomp.py -n ..\lib\stdlib.pas
+py pcomp.py -n stdlib.pas
 libgen ..\lib\stdlib.s
 libgen ..\lib\runtime.s
 libgen ..\lib\float32.s

rtl/arty-a7/tridoracpu.tcl

@@ -15,15 +15,56 @@
 #   run results please launch the synthesis/implementation runs as needed.
 #
 #*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (tridoracpu.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/cpuclk.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/display_clock.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/mem.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/stack.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/stackcpu.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/vgafb.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/top.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/testbench.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/rom.mem"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/ip/mig_dram_0/mig_a.prj"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/ip/mig_dram_0/mig_b.prj"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/dram_bridge.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/sdspi.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/bram_tdp.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/palette.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/irqctrl.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/fifo.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/fifo_testbench.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/sdspi_testbench.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/ip/mig_dram_0/mig_dram_0.xci"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sim_1/new/uart_tb.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/testbench_behav1.wcfg"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/fifo.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/new/fifo_testbench.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/sdspi_testbench_behav.wcfg"
+#
+# 3. The following remote source files that were added to the original project:-
+#
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/sources_1/imports/verilog/uart.v"
+#    "C:/Users/sebastian/develop/fpga/tridoracpu/tridoracpu.srcs/constrs_1/imports/fpga/Arty-A7-35-Master.xdc"
+#
+#*****************************************************************************************
 
-# uncomment next two statements if you have never initialized the Xilinx Board Store
-# this will take quite some time
 #xhub::refresh_catalog [xhub::get_xstores xilinx_board_store]
+# this will take quite some time
 #xhub::install [xhub::get_xitems]
 
-# Set the reference directory for source file relative paths
-set origin_dir "change_this_to_your_rtl_directory"
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "C:/Users/sebastian/develop/Tridora/rtl"
 
+# Oh come on, Xilinx, why?
+#set xilinx_board_store_dir "../../../../AppData/Roaming/Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store"
 set xilinx_board_store_dir [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]]
 set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]]