pcomp: Makefile bugfixes

doc/uart.md

@@ -37,7 +37,7 @@ It uses a fixed serial configuration of 115200 bps, 8 data bits, 1 stop bit, no
 
 
 ## Notes
-A 64 byte FIFO is used when receiving data.
+A 16 byte FIFO is used when receiving data.
 
 When reading data, each byte needs to be acknowledged by writing the _C_ flag to the UART register.
 

tridoracpu/tridoracpu.srcs/irqctrl.v

@@ -1,6 +1,6 @@
 `timescale 1ns / 1ps
 
-module irqctrl #(IRQ_LINES = 3, IRQ_DELAY_WIDTH = 8) (
+module irqctrl #(IRQ_LINES = 3, IRQ_DELAY_WIDTH = 4) (
         input wire clk,
         input wire [IRQ_LINES-1:0] irq_in,
         input wire cs,

tridoracpu/tridoracpu.srcs/stackcpu.v

@@ -399,10 +399,7 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
     // process irq
     always @(posedge clk)
     begin
-        // in MEM state, clear irq_pending, when nPC has been set to IV
+        if(seq_state == MEM && irq_pending && !(ins_xfer & xfer_r2p))   // in FETCH state, clear irq_pending.
-        // RET instruction is a special case because we need to use
-        // the new PC that is in mem_data
-        if(seq_state == MEM && irq_pending && !(ins_xfer && xfer_r2p))
             irq_pending <= 0;
         else
             irq_pending <= irq_pending || irq;  // else set irq_pending when irq is high

tridoracpu/tridoracpu.srcs/tdraudio.v

@@ -233,7 +233,7 @@ module tdraudio #(DATA_WIDTH=32) (
         chan2_rd_data, amp_wr_data,
         chan2_rd_en, chan2_wr_en,
         chan2_amp,
-        chan2_running, chan2_irq);
+        chan2_irq, chan2_running);
 
     wavegen chan3(clk, reset, reg_sel,
         chan3_rd_data, amp_wr_data,

tridoracpu/tridoracpu.srcs/top.v

@@ -278,9 +278,6 @@ module top(
                         (io_slot == 4) ? tdraudio_rd_data:
     `endif
                         -1;
-    irqctrl irqctrl0(`clock, irq_in, irqc_cs, mem_write_enable,
-            irqc_seten, irqc_rd_data0,
-            irq);
 
      // CPU -----------------------------------------------------------------
     stackcpu cpu0(.clk(`clock), .rst(rst), .irq(irq),
@@ -291,6 +288,10 @@ module top(
         .mem_wait(mem_wait),
         .debug1(led1), .debug2(led2), .debug3(led3));
 
+    // Interrupt Controller
+    irqctrl irqctrl0(`clock, irq_in, irqc_cs, mem_write_enable,
+            irqc_seten, irqc_rd_data0,
+            irq);
 
     // count clock ticks
     // generate interrupt every 20nth of a second

tridoracpu/tridoracpu.xpr

@@ -358,7 +358,9 @@
   <Runs Version="1" Minor="22">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -378,7 +380,9 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -387,7 +391,9 @@
         <Step Id="phys_opt_design"/>
         <Step Id="route_design"/>
         <Step Id="post_route_phys_opt_design"/>
-        <Step Id="write_bitstream"/>
+        <Step Id="write_bitstream">
+          <Option Id="BinFile">1</Option>
+        </Step>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
       <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>