import Vivado project, rearrange Verilog sources

README: small corrections

.gitignore

@@ -2,6 +2,7 @@ pcomp/*.s
 progs/*.s
 tests/*.s
 examples/*.s
+!runtime.s
 *.o
 *.exe
 *.bin
@@ -21,14 +22,18 @@ sine.pas
 graph1.pas
 graph2.pas
 chase.pas
-!runtime.s
+**/tridoracpu.cache/
-**/tridoracpu.*/
+**/tridoracpu.hw/
-rtl/arty-a7/mig_dram_0/_tmp/*
+**/tridoracpu.ip_user_files/
-rtl/arty-a7/mig_dram_0/doc/*
+**/tridoracpu.runs/
-rtl/arty-a7/mig_dram_0/mig_dram_0*
+*.log
-rtl/arty-a7/mig_dram_0/xil_txt.*
+*.jou
-rtl/arty-a7/mig_dram_0/*.veo
+**/mig_dram_0/_tmp/*
-rtl/arty-a7/mig_dram_0/*.tcl
+**/mig_dram_0/doc/*
-rtl/arty-a7/mig_dram_0/*.xml
+**/mig_dram_0/mig_dram_0*
-rtl/arty-a7/mig_dram_0/*.v
+**/mig_dram_0/xil_txt.*
-rtl/arty-a7/mig_dram_0/*.vhdl
+**/mig_dram_0/*.veo
+**/mig_dram_0/*.tcl
+**/mig_dram_0/*.xml
+**/mig_dram_0/*.v
+**/mig_dram_0/*.vhdl

README.md

@@ -6,7 +6,7 @@ Everything is as simple as possible while still being reasonably useful.
 Everything is open source, so you can read, understand and modify the whole system, hardware and software.
 
 ## Overview
-- Homebrew CPU
+- homebrew CPU
 - Verilog FPGA SoC
 - 32-bit word-oriented stack machine architecture
 - running at 83 MHz on an Arty-A7 board with four clocks per instruction
@@ -17,11 +17,11 @@ Everything is open source, so you can read, understand and modify the whole syst
 - minimal operating system
 - editor, compiler, assembler run natively
 - so you can develop programs directly on the machine
-- small: CPU has 760 lines of verilog, compiler ~9000 LoC
+- small: CPU has 430 lines of Verilog, compiler ~9000 LoC
-- Compiler written in Pascal and can compile itself
+- compiler written in Pascal and can compile itself
-- Cross-compiler/-assembler can be compiled with FPC
+- cross-compiler/-assembler can be compiled with FPC
-- Compiler does its own Pascal dialect with some restrictions and some extensions
+- compiler does its own Pascal dialect with some restrictions and some extensions
-- Emulator available
+- emulator available
 
 ## Demo
 - (Video hello world)
@@ -59,3 +59,11 @@ Everything is open source, so you can read, understand and modify the whole syst
 - most parts of the operating system are contained in the program image
 - file system is very primitive: only contiguous blocks, no subdirectories
 - simple shell reminiscent of TP3.0, edit, compile, run programs
+
+## Building the FPGA bitstream
+- install Vivado (tested with 2024.1)
+- install the package from your board in Vivado (Tools -> Vivado Store -> Boards)
+- run the project creation script in Vivado (Tools -> Run TCL Script -> open "tridoracpu.tcl" in the **rtl/arty-a7 directory**)
+- run synthesis, implementation and bitstream generation (Flow -> Generate Bitstream)
+- program your device (Flow -> Open Hardware Manager), the bitstream file should be in **rtl/arty-a7/tridoracpu.runs/impl_1**
+- the bitstream file for (temporarily) programming your device is named **top.bit**, the file for flashing your device is named **top.bin**

progs/editor.pas

@@ -390,8 +390,7 @@ begin
 	if numMode then
 		isValidChar := isDigit(ch)
 	else
-		isValidChar := (ord(ch) >= 32) and
+		isValidChar := (ord(ch) >= 32)
-			(ord(ch) <> 127); (* don't want DEL character *)
 end;
 
 begin
@@ -427,7 +426,7 @@ begin
 			c := chr(key);
 			l := length(strReturn);
 
-			if c = #8 then
+			if (c = #8) or (c = #127) then
 				doBackspace
 			else
 			if isValidChar(c) then

rtl/arty-a7/Arty_C_mig.ucf

@@ -1,48 +0,0 @@
-NET "ddr3_dq[0]"                             LOC = "K5"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[1]"                             LOC = "L3"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[2]"                             LOC = "K3"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[3]"                             LOC = "L6"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[4]"                             LOC = "M3"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[5]"                             LOC = "M1"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[6]"                             LOC = "L4"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[7]"                             LOC = "M2"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[8]"                             LOC = "V4"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[9]"                             LOC = "T5"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[10]"                            LOC = "U4"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[11]"                            LOC = "V5"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[12]"                            LOC = "V1"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[13]"                            LOC = "T3"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[14]"                            LOC = "U3"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dq[15]"                            LOC = "R3"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dm[0]"                             LOC = "L1"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dm[1]"                             LOC = "U1"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_dqs_p[0]"                          LOC = "N2"      |   IOSTANDARD = DIFF_SSTL135          ;                                 
-NET "ddr3_dqs_n[0]"                          LOC = "N1"      |   IOSTANDARD = DIFF_SSTL135          ;                                 
-NET "ddr3_dqs_p[1]"                          LOC = "U2"      |   IOSTANDARD = DIFF_SSTL135          ;                                 
-NET "ddr3_dqs_n[1]"                          LOC = "V2"      |   IOSTANDARD = DIFF_SSTL135          ;                                 
-NET "ddr3_addr[13]"                          LOC = "T8"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_addr[12]"                          LOC = "T6"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_addr[11]"                          LOC = "U6"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_addr[10]"                          LOC = "R6"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_addr[9]"                           LOC = "V7"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_addr[8]"                           LOC = "R8"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_addr[7]"                           LOC = "U7"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_addr[6]"                           LOC = "V6"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_addr[5]"                           LOC = "R7"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_addr[4]"                           LOC = "N6"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_addr[3]"                           LOC = "T1"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_addr[2]"                           LOC = "N4"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_addr[1]"                           LOC = "M6"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_addr[0]"                           LOC = "R2"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_ba[2]"                             LOC = "P2"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_ba[1]"                             LOC = "P4"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_ba[0]"                             LOC = "R1"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_ck_p[0]"                           LOC = "U9"      |   IOSTANDARD = DIFF_SSTL135          ;                                 
-NET "ddr3_ck_n[0]"                           LOC = "V9"      |   IOSTANDARD = DIFF_SSTL135          ;                                 
-NET "ddr3_ras_n"                             LOC = "P3"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_cas_n"                             LOC = "M4"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_we_n"                              LOC = "P5"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_reset_n"                           LOC = "K6"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_cke[0]"                            LOC = "N5"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_odt[0]"                            LOC = "R5"      |   IOSTANDARD = SSTL135               ;                                 
-NET "ddr3_cs_n[0]"                           LOC = "U8"      |   IOSTANDARD = SSTL135               ;                                 

rtl/arty-a7/tridoracpu.tcl

@@ -1,683 +0,0 @@
-#*****************************************************************************************
-# Vivado (TM) v2020.1 (64-bit)
-#
-# tridoracpu.tcl: Tcl script for re-creating project 'tridoracpu'
-#
-# Generated by Vivado on Sat Sep 14 23:58:12 +0200 2024
-# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
-#
-# This file contains the Vivado Tcl commands for re-creating the project to the state*
-# when this script was generated. In order to re-create the project, please source this
-# file in the Vivado Tcl Shell.
-#
-# * Note that the runs in the created project will be configured the same way as the
-#   original project, however they will not be launched automatically. To regenerate the
-#   run results please launch the synthesis/implementation runs as needed.
-#
-#*****************************************************************************************
-
-# uncomment next two statements if you have never initialized the Xilinx Board Store
-# this will take quite some time
-#xhub::refresh_catalog [xhub::get_xstores xilinx_board_store]
-#xhub::install [xhub::get_xitems]
-
-# Set the reference directory for source file relative paths
-set origin_dir "change_this_to_your_rtl_directory"
-
-set xilinx_board_store_dir [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]]
-set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]]
-
-# Use origin directory path location variable, if specified in the tcl shell
-if { [info exists ::origin_dir_loc] } {
-  set origin_dir $::origin_dir_loc
-}
-
-# Set the project name
-set _xil_proj_name_ "tridoracpu"
-
-# Use project name variable, if specified in the tcl shell
-if { [info exists ::user_project_name] } {
-  set _xil_proj_name_ $::user_project_name
-}
-
-variable script_file
-set script_file "tridoracpu.tcl"
-
-# Help information for this script
-proc print_help {} {
-  variable script_file
-  puts "\nDescription:"
-  puts "Recreate a Vivado project from this script. The created project will be"
-  puts "functionally equivalent to the original project for which this script was"
-  puts "generated. The script contains commands for creating a project, filesets,"
-  puts "runs, adding/importing sources and setting properties on various objects.\n"
-  puts "Syntax:"
-  puts "$script_file"
-  puts "$script_file -tclargs \[--origin_dir <path>\]"
-  puts "$script_file -tclargs \[--project_name <name>\]"
-  puts "$script_file -tclargs \[--help\]\n"
-  puts "Usage:"
-  puts "Name                   Description"
-  puts "-------------------------------------------------------------------------"
-  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
-  puts "                       origin_dir path value is \".\", otherwise, the value"
-  puts "                       that was set with the \"-paths_relative_to\" switch"
-  puts "                       when this script was generated.\n"
-  puts "\[--project_name <name>\] Create project with the specified name. Default"
-  puts "                       name is the name of the project from where this"
-  puts "                       script was generated.\n"
-  puts "\[--help\]               Print help information for this script"
-  puts "-------------------------------------------------------------------------\n"
-  exit 0
-}
-
-if { $::argc > 0 } {
-  for {set i 0} {$i < $::argc} {incr i} {
-    set option [string trim [lindex $::argv $i]]
-    switch -regexp -- $option {
-      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
-      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
-      "--help"         { print_help }
-      default {
-        if { [regexp {^-} $option] } {
-          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
-          return 1
-        }
-      }
-    }
-  }
-}
-
-# Set the directory path for the original project from where this script was exported
-set orig_proj_dir "[file normalize "${origin_dir}/arty-a7"]"
-
-# Create project
-create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a35ticsg324-1L
-
-# Set the directory path for the new project
-set proj_dir [get_property directory [current_project]]
-
-# Set project properties
-set obj [current_project]
-#set_property -name "board_part_repo_paths" -value "[file normalize "$xilinx_board_store_dir"]" -objects $obj
-set_property -name "board_part" -value "digilentinc.com:arty-a7-35:part0:1.0" -objects $obj
-set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
-set_property -name "enable_vhdl_2008" -value "1" -objects $obj
-set_property -name "ip_cache_permissions" -value "read write" -objects $obj
-set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
-set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
-set_property -name "platform.board_id" -value "arty-a7-35" -objects $obj
-set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
-set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
-set_property -name "simulator_language" -value "Mixed" -objects $obj
-set_property -name "source_mgmt_mode" -value "DisplayOnly" -objects $obj
-set_property -name "webtalk.activehdl_export_sim" -value "4" -objects $obj
-set_property -name "webtalk.ies_export_sim" -value "4" -objects $obj
-set_property -name "webtalk.modelsim_export_sim" -value "4" -objects $obj
-set_property -name "webtalk.questa_export_sim" -value "4" -objects $obj
-set_property -name "webtalk.riviera_export_sim" -value "4" -objects $obj
-set_property -name "webtalk.vcs_export_sim" -value "4" -objects $obj
-set_property -name "webtalk.xsim_export_sim" -value "4" -objects $obj
-set_property -name "webtalk.xsim_launch_sim" -value "537" -objects $obj
-
-# Create 'sources_1' fileset (if not found)
-if {[string equal [get_filesets -quiet sources_1] ""]} {
-  create_fileset -srcset sources_1
-}
-
-# Set 'sources_1' fileset object
-set obj [get_filesets sources_1]
-set files [list \
- [file normalize "${origin_dir}/src/uart.v"] \
-]
-add_files -norecurse -fileset $obj $files
-
-# Add local files from the original project (-no_copy_sources specified)
-set files [list \
- [file normalize "${origin_dir}/src/cpuclk.v" ]\
- [file normalize "${origin_dir}/src/display_clock.v" ]\
- [file normalize "${origin_dir}/src/mem.v" ]\
- [file normalize "${origin_dir}/src/stack.v" ]\
- [file normalize "${origin_dir}/src/stackcpu.v" ]\
- [file normalize "${origin_dir}/src/vgafb.v" ]\
- [file normalize "${origin_dir}/src/top.v" ]\
- [file normalize "${origin_dir}/src/testbench.v" ]\
- [file normalize "${orig_proj_dir}/rom.mem" ]\
- [file normalize "${orig_proj_dir}/mig_dram_0/mig_a.prj" ]\
- [file normalize "${orig_proj_dir}/mig_dram_0/mig_b.prj" ]\
- [file normalize "${origin_dir}/src/dram_bridge.v" ]\
- [file normalize "${origin_dir}/src/sdspi.v" ]\
- [file normalize "${origin_dir}/src/bram_tdp.v" ]\
- [file normalize "${origin_dir}/src/palette.v" ]\
- [file normalize "${origin_dir}/src/irqctrl.v" ]\
- [file normalize "${origin_dir}/src/fifo.v" ]\
- [file normalize "${origin_dir}/src/fifo_testbench.v" ]\
- [file normalize "${origin_dir}/src/sdspi_testbench.v" ]\
-]
-set added_files [add_files -fileset sources_1 $files]
-
-# Set 'sources_1' fileset file properties for remote files
-set file "$origin_dir/src/uart.v"
-set file [file normalize $file]
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
-set_property -name "used_in_simulation" -value "0" -objects $file_obj
-
-
-# Set 'sources_1' fileset file properties for local files
-set file "src/cpuclk.v"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
-set_property -name "used_in_simulation" -value "0" -objects $file_obj
-
-set file "src/display_clock.v"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "is_enabled" -value "0" -objects $file_obj
-
-set file "src/mem.v"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
-set_property -name "used_in_simulation" -value "0" -objects $file_obj
-
-set file "src/stack.v"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
-set_property -name "used_in_simulation" -value "0" -objects $file_obj
-
-set file "src/stackcpu.v"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
-set_property -name "used_in_simulation" -value "0" -objects $file_obj
-
-set file "src/vgafb.v"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
-set_property -name "used_in_simulation" -value "0" -objects $file_obj
-
-set file "src/top.v"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
-set_property -name "used_in_simulation" -value "0" -objects $file_obj
-
-set file "src/testbench.v"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "" -objects $file_obj
-set_property -name "used_in_implementation" -value "0" -objects $file_obj
-set_property -name "used_in_simulation" -value "0" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "arty-a7/rom.mem"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "file_type" -value "Memory File" -objects $file_obj
-
-set file "arty-a7/mig_dram_0/mig_a.prj"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "scoped_to_cells" -value "mig_dram_0" -objects $file_obj
-
-set file "arty-a7/mig_dram_0/mig_b.prj"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "scoped_to_cells" -value "mig_dram_0" -objects $file_obj
-
-set file "src/dram_bridge.v"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
-set_property -name "used_in_simulation" -value "0" -objects $file_obj
-
-set file "src/palette.v"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
-set_property -name "used_in_simulation" -value "0" -objects $file_obj
-
-set file "src/irqctrl.v"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
-set_property -name "used_in_simulation" -value "0" -objects $file_obj
-
-set file "src/fifo_testbench.v"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "" -objects $file_obj
-set_property -name "used_in_implementation" -value "0" -objects $file_obj
-set_property -name "used_in_simulation" -value "0" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-
-# Set 'sources_1' fileset properties
-set obj [get_filesets sources_1]
-set_property -name "top" -value "top" -objects $obj
-set_property -name "top_auto_set" -value "0" -objects $obj
-
-# Set 'sources_1' fileset object
-set obj [get_filesets sources_1]
-# Add local files from the original project (-no_copy_sources specified)
-set files [list \
- [file normalize "${orig_proj_dir}/mig_dram_0/mig_dram_0.xci" ]\
-]
-set added_files [add_files -fileset sources_1 $files]
-
-# Set 'sources_1' fileset file properties for remote files
-# None
-
-# Set 'sources_1' fileset file properties for local files
-set file "arty-a7/mig_dram_0/mig_dram_0.xci"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
-set_property -name "registered_with_manager" -value "1" -objects $file_obj
-if { ![get_property "is_locked" $file_obj] } {
-  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
-}
-set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
-set_property -name "used_in_simulation" -value "0" -objects $file_obj
-
-
-# Create 'constrs_1' fileset (if not found)
-if {[string equal [get_filesets -quiet constrs_1] ""]} {
-  create_fileset -constrset constrs_1
-}
-
-# Set 'constrs_1' fileset object
-set obj [get_filesets constrs_1]
-
-# Add/Import constrs file and set constrs file properties
-set file "[file normalize ${origin_dir}/arty-a7/Arty-A7-35-Master.xdc]"
-set file_added [add_files -norecurse -fileset $obj [list $file]]
-set file "$origin_dir/arty-a7/Arty-A7-35-Master.xdc"
-set file [file normalize $file]
-set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
-set_property -name "file_type" -value "XDC" -objects $file_obj
-
-# Set 'constrs_1' fileset properties
-set obj [get_filesets constrs_1]
-set_property -name "target_constrs_file" -value "$orig_proj_dir/Arty-A7-35-Master.xdc" -objects $obj
-set_property -name "target_ucf" -value "$orig_proj_dir/Arty-A7-35-Master.xdc" -objects $obj
-
-# Create 'sim_1' fileset (if not found)
-if {[string equal [get_filesets -quiet sim_1] ""]} {
-  create_fileset -simset sim_1
-}
-
-# Set 'sim_1' fileset object
-set obj [get_filesets sim_1]
-# Add local files from the original project (-no_copy_sources specified)
-set files [list \
- [file normalize "${origin_dir}/src/uart_tb.v" ]\
- [file normalize "${orig_proj_dir}/testbench_behav1.wcfg" ]\
-]
-set added_files [add_files -fileset sim_1 $files]
-
-# Set 'sim_1' fileset file properties for remote files
-# None
-
-# Set 'sim_1' fileset file properties for local files
-set file [file normalize "${origin_dir}/src/uart_tb.v"]
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "used_in" -value "" -objects $file_obj
-set_property -name "used_in_implementation" -value "0" -objects $file_obj
-set_property -name "used_in_simulation" -value "0" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-
-# Set 'sim_1' fileset properties
-set obj [get_filesets sim_1]
-set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
-set_property -name "nl.mode" -value "funcsim" -objects $obj
-set_property -name "top" -value "testbench" -objects $obj
-set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
-
-# Create 'sim_fifo' fileset (if not found)
-if {[string equal [get_filesets -quiet sim_fifo] ""]} {
-  create_fileset -simset sim_fifo
-}
-
-# Set 'sim_fifo' fileset object
-set obj [get_filesets sim_fifo]
-# Add local files from the original project (-no_copy_sources specified)
-set files [list \
- [file normalize "${origin_dir}/src/fifo.v" ]\
- [file normalize "${origin_dir}/src/fifo_testbench.v" ]\
-]
-set added_files [add_files -fileset sim_fifo $files]
-
-# Set 'sim_fifo' fileset file properties for remote files
-# None
-
-# Set 'sim_fifo' fileset file properties for local files
-# None
-
-# Set 'sim_fifo' fileset properties
-set obj [get_filesets sim_fifo]
-set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
-set_property -name "top" -value "fifo_testbench" -objects $obj
-set_property -name "top_auto_set" -value "0" -objects $obj
-
-# Create 'sim_sdspi' fileset (if not found)
-if {[string equal [get_filesets -quiet sim_sdspi] ""]} {
-  create_fileset -simset sim_sdspi
-}
-
-# Set 'sim_sdspi' fileset object
-set obj [get_filesets sim_sdspi]
-# Add local files from the original project (-no_copy_sources specified)
-set files [list \
- [file normalize "${orig_proj_dir}/sdspi_testbench_behav.wcfg" ]\
-]
-set added_files [add_files -fileset sim_sdspi $files]
-
-# Set 'sim_sdspi' fileset file properties for remote files
-# None
-
-# Set 'sim_sdspi' fileset file properties for local files
-# None
-
-# Set 'sim_sdspi' fileset properties
-set obj [get_filesets sim_sdspi]
-set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
-set_property -name "sim_mode" -value "post-synthesis" -objects $obj
-set_property -name "top" -value "sdspi_testbench" -objects $obj
-set_property -name "top_auto_set" -value "0" -objects $obj
-set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
-set_property -name "xsim.simulate.runtime" -value "10ms" -objects $obj
-
-# Set 'utils_1' fileset object
-set obj [get_filesets utils_1]
-# Empty (no sources present)
-
-# Set 'utils_1' fileset properties
-set obj [get_filesets utils_1]
-
-# Create 'synth_1' run (if not found)
-if {[string equal [get_runs -quiet synth_1] ""]} {
-    create_run -name synth_1 -part xc7a35ticsg324-1L -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
-} else {
-  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
-  set_property flow "Vivado Synthesis 2020" [get_runs synth_1]
-}
-set obj [get_runs synth_1]
-set_property set_report_strategy_name 1 $obj
-set_property report_strategy {Vivado Synthesis Default Reports} $obj
-set_property set_report_strategy_name 0 $obj
-# Create 'synth_1_synth_report_utilization_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
-  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
-}
-set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
-if { $obj != "" } {
-
-}
-set obj [get_runs synth_1]
-set_property -name "needs_refresh" -value "1" -objects $obj
-set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
-
-# set the current synth run
-current_run -synthesis [get_runs synth_1]
-
-# Create 'impl_1' run (if not found)
-if {[string equal [get_runs -quiet impl_1] ""]} {
-    create_run -name impl_1 -part xc7a35ticsg324-1L -flow {Vivado Implementation 2020} -strategy "Performance_RefinePlacement" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
-} else {
-  set_property strategy "Performance_RefinePlacement" [get_runs impl_1]
-  set_property flow "Vivado Implementation 2020" [get_runs impl_1]
-}
-set obj [get_runs impl_1]
-set_property set_report_strategy_name 1 $obj
-set_property report_strategy {Vivado Implementation Default Reports} $obj
-set_property set_report_strategy_name 0 $obj
-# Create 'impl_1_init_report_timing_summary_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
-  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
-if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
-set_property -name "options.max_paths" -value "10" -objects $obj
-
-}
-# Create 'impl_1_opt_report_drc_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
-  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
-if { $obj != "" } {
-
-}
-# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
-  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
-if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
-set_property -name "options.max_paths" -value "10" -objects $obj
-
-}
-# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
-  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
-if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
-set_property -name "options.max_paths" -value "10" -objects $obj
-
-}
-# Create 'impl_1_place_report_io_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
-  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
-if { $obj != "" } {
-
-}
-# Create 'impl_1_place_report_utilization_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
-  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
-if { $obj != "" } {
-
-}
-# Create 'impl_1_place_report_control_sets_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
-  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
-if { $obj != "" } {
-set_property -name "options.verbose" -value "1" -objects $obj
-
-}
-# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
-  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
-if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
-
-}
-# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
-  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
-if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
-
-}
-# Create 'impl_1_place_report_timing_summary_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
-  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
-if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
-set_property -name "options.max_paths" -value "10" -objects $obj
-
-}
-# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
-  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
-if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
-set_property -name "options.max_paths" -value "10" -objects $obj
-
-}
-# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
-  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
-if { $obj != "" } {
-set_property -name "is_enabled" -value "0" -objects $obj
-set_property -name "options.max_paths" -value "10" -objects $obj
-
-}
-# Create 'impl_1_route_report_drc_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
-  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
-if { $obj != "" } {
-
-}
-# Create 'impl_1_route_report_methodology_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
-  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
-if { $obj != "" } {
-
-}
-# Create 'impl_1_route_report_power_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
-  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
-if { $obj != "" } {
-
-}
-# Create 'impl_1_route_report_route_status_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
-  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
-if { $obj != "" } {
-
-}
-# Create 'impl_1_route_report_timing_summary_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
-  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
-if { $obj != "" } {
-set_property -name "options.max_paths" -value "10" -objects $obj
-
-}
-# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
-  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
-if { $obj != "" } {
-
-}
-# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
-  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
-if { $obj != "" } {
-
-}
-# Create 'impl_1_route_report_bus_skew_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
-  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
-if { $obj != "" } {
-set_property -name "options.warn_on_violation" -value "1" -objects $obj
-
-}
-# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
-  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
-if { $obj != "" } {
-set_property -name "options.max_paths" -value "10" -objects $obj
-set_property -name "options.warn_on_violation" -value "1" -objects $obj
-
-}
-# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
-if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
-  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
-}
-set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
-if { $obj != "" } {
-set_property -name "options.warn_on_violation" -value "1" -objects $obj
-
-}
-set obj [get_runs impl_1]
-set_property -name "needs_refresh" -value "1" -objects $obj
-set_property -name "strategy" -value "Performance_RefinePlacement" -objects $obj
-set_property -name "steps.place_design.args.directive" -value "ExtraPostPlacementOpt" -objects $obj
-set_property -name "steps.phys_opt_design.args.directive" -value "Explore" -objects $obj
-set_property -name "steps.route_design.args.directive" -value "Explore" -objects $obj
-set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj
-set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
-set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
-
-# set the current impl run
-current_run -implementation [get_runs impl_1]
-
-puts "INFO: Project created:${_xil_proj_name_}"
-# Create 'drc_1' gadget (if not found)
-if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
-create_dashboard_gadget -name {drc_1} -type drc
-}
-set obj [get_dashboard_gadgets [ list "drc_1" ] ]
-set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
-
-# Create 'methodology_1' gadget (if not found)
-if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
-create_dashboard_gadget -name {methodology_1} -type methodology
-}
-set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
-set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
-
-# Create 'power_1' gadget (if not found)
-if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
-create_dashboard_gadget -name {power_1} -type power
-}
-set obj [get_dashboard_gadgets [ list "power_1" ] ]
-set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
-
-# Create 'timing_1' gadget (if not found)
-if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
-create_dashboard_gadget -name {timing_1} -type timing
-}
-set obj [get_dashboard_gadgets [ list "timing_1" ] ]
-set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
-
-# Create 'utilization_1' gadget (if not found)
-if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
-create_dashboard_gadget -name {utilization_1} -type utilization
-}
-set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
-set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
-set_property -name "run.step" -value "synth_design" -objects $obj
-set_property -name "run.type" -value "synthesis" -objects $obj
-
-# Create 'utilization_2' gadget (if not found)
-if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
-create_dashboard_gadget -name {utilization_2} -type utilization
-}
-set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
-set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
-
-move_dashboard_gadget -name {utilization_1} -row 0 -col 0
-move_dashboard_gadget -name {power_1} -row 1 -col 0
-move_dashboard_gadget -name {drc_1} -row 2 -col 0
-move_dashboard_gadget -name {timing_1} -row 0 -col 1
-move_dashboard_gadget -name {utilization_2} -row 1 -col 1
-move_dashboard_gadget -name {methodology_1} -row 2 -col 1

tridoracpu/testbench_behav.wcfg

@@ -0,0 +1,272 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="testbench_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="testbench" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0fs"></ZoomStartTime>
+      <ZoomEndTime time="516271fs"></ZoomEndTime>
+      <Cursor1Time time="48444fs"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="240"></NameColumnWidth>
+      <ValueColumnWidth column_width="90"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="39" />
+   <wvobject fp_name="/testbench/uut/seq_state" type="array">
+      <obj_property name="ElementShortName">seq_state[1:0]</obj_property>
+      <obj_property name="ObjectShortName">seq_state[1:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/PC" type="array">
+      <obj_property name="ElementShortName">PC[15:0]</obj_property>
+      <obj_property name="ObjectShortName">PC[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="CustomSignalColor">#D2691E</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/nPC" type="array">
+      <obj_property name="ElementShortName">nPC[15:0]</obj_property>
+      <obj_property name="ObjectShortName">nPC[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="CustomSignalColor">#D2691E</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/ins" type="array">
+      <obj_property name="ElementShortName">ins[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ins[15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#D2691E</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/operand" type="array">
+      <obj_property name="ElementShortName">operand[15:0]</obj_property>
+      <obj_property name="ObjectShortName">operand[15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#D2691E</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/ins_branch" type="logic">
+      <obj_property name="ElementShortName">ins_branch</obj_property>
+      <obj_property name="ObjectShortName">ins_branch</obj_property>
+      <obj_property name="CustomSignalColor">#D2691E</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/ins_cbranch" type="logic">
+      <obj_property name="ElementShortName">ins_cbranch</obj_property>
+      <obj_property name="ObjectShortName">ins_cbranch</obj_property>
+      <obj_property name="CustomSignalColor">#D2691E</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/ins_load" type="logic">
+      <obj_property name="ElementShortName">ins_load</obj_property>
+      <obj_property name="ObjectShortName">ins_load</obj_property>
+      <obj_property name="CustomSignalColor">#D2691E</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/ins_loadc" type="logic">
+      <obj_property name="ElementShortName">ins_loadc</obj_property>
+      <obj_property name="ObjectShortName">ins_loadc</obj_property>
+      <obj_property name="CustomSignalColor">#D2691E</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/ins_loadi" type="logic">
+      <obj_property name="ElementShortName">ins_loadi</obj_property>
+      <obj_property name="ObjectShortName">ins_loadi</obj_property>
+      <obj_property name="CustomSignalColor">#D2691E</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/ins_loadim" type="logic">
+      <obj_property name="ElementShortName">ins_loadim</obj_property>
+      <obj_property name="ObjectShortName">ins_loadim</obj_property>
+      <obj_property name="CustomSignalColor">#D2691E</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/ins_store" type="logic">
+      <obj_property name="ElementShortName">ins_store</obj_property>
+      <obj_property name="ObjectShortName">ins_store</obj_property>
+      <obj_property name="CustomSignalColor">#A52A2A</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/ins_aluop" type="logic">
+      <obj_property name="ElementShortName">ins_aluop</obj_property>
+      <obj_property name="ObjectShortName">ins_aluop</obj_property>
+      <obj_property name="CustomSignalColor">#D2691E</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/aluop" type="array">
+      <obj_property name="ElementShortName">aluop[3:0]</obj_property>
+      <obj_property name="ObjectShortName">aluop[3:0]</obj_property>
+      <obj_property name="CustomSignalColor">#FFD700</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="Radix">BINARYRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/aluop_sd" type="array">
+      <obj_property name="ElementShortName">aluop_sd[1:0]</obj_property>
+      <obj_property name="ObjectShortName">aluop_sd[1:0]</obj_property>
+      <obj_property name="CustomSignalColor">#FFD700</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/aluop_x2y" type="logic">
+      <obj_property name="ElementShortName">aluop_x2y</obj_property>
+      <obj_property name="ObjectShortName">aluop_x2y</obj_property>
+      <obj_property name="CustomSignalColor">#FFD700</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/mem_addr" type="array">
+      <obj_property name="ElementShortName">mem_addr[15:0]</obj_property>
+      <obj_property name="ObjectShortName">mem_addr[15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#DCDCDC</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/mem_read_enable" type="logic">
+      <obj_property name="ElementShortName">mem_read_enable</obj_property>
+      <obj_property name="ObjectShortName">mem_read_enable</obj_property>
+      <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/mem_read_data" type="array">
+      <obj_property name="ElementShortName">mem_read_data[15:0]</obj_property>
+      <obj_property name="ObjectShortName">mem_read_data[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/mem_write_enable" type="logic">
+      <obj_property name="ElementShortName">mem_write_enable</obj_property>
+      <obj_property name="ObjectShortName">mem_write_enable</obj_property>
+      <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/mem_write_data" type="array">
+      <obj_property name="ElementShortName">mem_write_data[15:0]</obj_property>
+      <obj_property name="ObjectShortName">mem_write_data[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/X" type="array">
+      <obj_property name="ElementShortName">X[15:0]</obj_property>
+      <obj_property name="ObjectShortName">X[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="CustomSignalColor">#FF0080</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/nX" type="array">
+      <obj_property name="ElementShortName">nX[15:0]</obj_property>
+      <obj_property name="ObjectShortName">nX[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="CustomSignalColor">#FF0080</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/Y" type="array">
+      <obj_property name="ElementShortName">Y[15:0]</obj_property>
+      <obj_property name="ObjectShortName">Y[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="CustomSignalColor">#FF0080</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/FP" type="array">
+      <obj_property name="ElementShortName">FP[15:0]</obj_property>
+      <obj_property name="ObjectShortName">FP[15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#DCDCDC</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/BP" type="array">
+      <obj_property name="ElementShortName">BP[15:0]</obj_property>
+      <obj_property name="ObjectShortName">BP[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="CustomSignalColor">#DCDCDC</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/RP" type="array">
+      <obj_property name="ElementShortName">RP[15:0]</obj_property>
+      <obj_property name="ObjectShortName">RP[15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/nRP" type="array">
+      <obj_property name="ElementShortName">nRP[15:0]</obj_property>
+      <obj_property name="ObjectShortName">nRP[15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/ESP" type="array">
+      <obj_property name="ElementShortName">ESP[5:0]</obj_property>
+      <obj_property name="ObjectShortName">ESP[5:0]</obj_property>
+      <obj_property name="CustomSignalColor">#008080</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/nESP" type="array">
+      <obj_property name="ElementShortName">nESP[5:0]</obj_property>
+      <obj_property name="ObjectShortName">nESP[5:0]</obj_property>
+      <obj_property name="CustomSignalColor">#008080</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/stack_write" type="logic">
+      <obj_property name="ElementShortName">stack_write</obj_property>
+      <obj_property name="ObjectShortName">stack_write</obj_property>
+      <obj_property name="CustomSignalColor">#008080</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/estack/stack[0]" type="array">
+      <obj_property name="ElementShortName">[0][15:0]</obj_property>
+      <obj_property name="ObjectShortName">[0][15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/estack/stack[1]" type="array">
+      <obj_property name="ElementShortName">[1][15:0]</obj_property>
+      <obj_property name="ObjectShortName">[1][15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/estack/stack[2]" type="array">
+      <obj_property name="ElementShortName">[2][15:0]</obj_property>
+      <obj_property name="ObjectShortName">[2][15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/estack/stack[3]" type="array">
+      <obj_property name="ElementShortName">[3][15:0]</obj_property>
+      <obj_property name="ObjectShortName">[3][15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/estack/stack[4]" type="array">
+      <obj_property name="ElementShortName">[4][15:0]</obj_property>
+      <obj_property name="ObjectShortName">[4][15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/estack/stack[5]" type="array">
+      <obj_property name="ElementShortName">[5][15:0]</obj_property>
+      <obj_property name="ObjectShortName">[5][15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/estack/stack[6]" type="array">
+      <obj_property name="ElementShortName">[6][15:0]</obj_property>
+      <obj_property name="ObjectShortName">[6][15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/estack/stack[7]" type="array">
+      <obj_property name="ElementShortName">[7][15:0]</obj_property>
+      <obj_property name="ObjectShortName">[7][15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+</wave_config>

tridoracpu/tridoracpu.srcs/sfifo.v

@@ -0,0 +1,84 @@
+`timescale 1ns / 1ps
+
+// a simple fifo
+module fifo #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 4)(
+    input wire clk,
+    input wire reset,
+    input wire wr_en,
+    input wire rd_en,
+    input wire [DATA_WIDTH-1:0] wr_data,
+    output wire [DATA_WIDTH-1:0] rd_data,
+    output wire wr_full,
+    output wire rd_empty
+    );
+
+    reg [DATA_WIDTH-1:0] mem [0:ADDR_WIDTH-1];
+    reg [ADDR_WIDTH:0]  head_x = 0;  // head and tail have one extra bit 
+    reg [ADDR_WIDTH:0]  tail_x = 0;  // for detecting overflows
+    wire [ADDR_WIDTH-1:0] head = head_x[ADDR_WIDTH-1:0];
+    wire [ADDR_WIDTH-1:0] tail = tail_x[ADDR_WIDTH-1:0];
+    
+    assign rd_data = mem[tail];
+    // the fifo is full when head and tail pointer are the same
+    // and the extra bits differ (a wraparound occured)
+    assign wr_full = (head == tail) && (head_x[ADDR_WIDTH] != tail_x[ADDR_WIDTH]);
+    // the fifo is empty when head and tail pointer are the same
+    // and the extra bits are the same (no wraparound)
+    assign rd_empty = (head == tail) && (head_x[ADDR_WIDTH] == tail_x[ADDR_WIDTH]);
+  
+    // Writing to FIFO
+    always @(posedge clk) begin
+        if (wr_en)
+        begin
+            mem[head[ADDR_WIDTH-1:0]] <= wr_data;
+            // move head, possible wraparound
+            head_x <= head_x + 1'b1;
+        end
+    end
+
+    // Reading from FIFO
+    always @(posedge clk)
+    begin
+        if (rd_en)
+        begin
+            // rd_data always has current tail data
+            // move tail, possible wraparound
+            tail <= tail + 1'b1;
+        end
+    end
+
+    // Calculating full/empty flags, referenced from zipcpu.com
+    wire	[c_DEPTH:0]	dblnext, nxtread;
+    assign	dblnext = wraddr + 2;
+    assign	nxtread = rdaddr + 1'b1;
+
+    always @(posedge i_Clock, negedge i_Reset)
+    
+        // Reset case
+        if (!i_Reset)
+        begin
+            // Reset output flags
+            fifo_full <= 1'b0;
+            fifo_empty <= 1'b1;
+            
+        end else casez({ i_Write_En, i_Read_En, !fifo_full, !fifo_empty })
+        4'b01?1: begin	// A successful read
+            fifo_full  <= 1'b0;
+            fifo_empty <= (nxtread == wraddr);
+        end
+        4'b101?: begin	// A successful write
+            fifo_full <= (dblnext == rdaddr);
+            fifo_empty <= 1'b0;
+        end
+        4'b11?0: begin	// Successful write, failed read
+            fifo_full  <= 1'b0;
+            fifo_empty <= 1'b0;
+        end
+        4'b11?1: begin	// Successful read and write
+            fifo_full  <= fifo_full;
+            fifo_empty <= 1'b0;
+        end
+        default: begin end
+        endcase
+    
+endmodule

tridoracpu/tridoracpu.xpr

@@ -0,0 +1,417 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.1 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="49" Path="./tridoracpu.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="ab60beb5e7ec4efc9a7b17699b9c3b13"/>
+    <Option Name="Part" Val="xc7a35ticsg324-1L"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirIES" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="BoardPart" Val="digilentinc.com:arty-a7-35:part0:1.0"/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../AppData/Roaming/Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store"/>
+    <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
+    <Option Name="ActiveSimSet" Val="sim_sdspi"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PSRCDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSABoardId" Val="arty-a7-35"/>
+    <Option Name="WTXSimLaunchSim" Val="537"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="4"/>
+    <Option Name="WTModelSimExportSim" Val="4"/>
+    <Option Name="WTQuestaExportSim" Val="4"/>
+    <Option Name="WTIesExportSim" Val="4"/>
+    <Option Name="WTVcsExportSim" Val="4"/>
+    <Option Name="WTRivieraExportSim" Val="4"/>
+    <Option Name="WTActivehdlExportSim" Val="4"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/cpuclk.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/display_clock.v">
+        <FileInfo>
+          <Attr Name="UserDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
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+      </File>
+      <File Path="$PSRCDIR/mem.v">
+        <FileInfo>
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+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/stack.v">
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+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/stackcpu.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/uart.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/vgafb.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/top.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/testbench.v"/>
+      <File Path="$PPRDIR/rom.mem">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/mig_dram_0/mig_a.prj">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="ScopedToCell" Val="mig_dram_0"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/mig_dram_0/mig_b.prj">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="ScopedToCell" Val="mig_dram_0"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/dram_bridge.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sdspi.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/bram_tdp.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/palette.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/irqctrl.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/fifo.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/fifo_testbench.v"/>
+      <File Path="$PSRCDIR/sdspi_testbench.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="top"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR">
+      <Filter Type="Constrs"/>
+      <File Path="$PSRCDIR/Arty-A7-35-Master.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PSRCDIR/Arty-A7-35-Master.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/uart_tb.v"/>
+      <File Path="$PPRDIR/testbench_behav1.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="testbench"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/testbench_behav.wcfg"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/testbench_behav1.wcfg"/>
+        <Option Name="NLNetlistMode" Val="funcsim"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="mig_dram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/mig_dram_0">
+      <File Path="$PSRCDIR/mig_dram_0/mig_dram_0.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="mig_dram_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_fifo" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_fifo">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/fifo.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/fifo_testbench.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="fifo_testbench"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_sdspi" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_sdspi">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/sdspi_testbench_behav.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="sdspi_testbench"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="SimMode" Val="post-synthesis"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/sdspi_testbench_behav.wcfg"/>
+        <Option Name="xsim.simulate.runtime" Val="10ms"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="11">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Increase placer effort in the post-placement optimization phase, and disable timing relaxation in the router." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Performance_RefinePlacement" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design">
+          <Option Id="Directive">7</Option>
+        </Step>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design">
+          <Option Id="Directive">0</Option>
+        </Step>
+        <Step Id="route_design">
+          <Option Id="Directive">0</Option>
+        </Step>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream">
+          <Option Id="BinFile">1</Option>
+        </Step>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>