From 12033bb6d24387658c85b5042724ad564ac5223f Mon Sep 17 00:00:00 2001 From: slederer Date: Mon, 29 Sep 2025 19:10:48 +0200 Subject: [PATCH 1/2] tdraudio: add direct amplitude control --- tridoracpu/tridoracpu.srcs/tdraudio.v | 29 ++++++++++++++++++++------- tridoracpu/tridoracpu.xpr | 12 +++++++---- 2 files changed, 30 insertions(+), 11 deletions(-) diff --git a/tridoracpu/tridoracpu.srcs/tdraudio.v b/tridoracpu/tridoracpu.srcs/tdraudio.v index 5c19264..9cb1d74 100644 --- a/tridoracpu/tridoracpu.srcs/tdraudio.v +++ b/tridoracpu/tridoracpu.srcs/tdraudio.v @@ -42,17 +42,22 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) ( reg [LFSR_WIDTH-1:0] lfsr; wire [AMP_WIDTH-1:0] noise_out; + reg direct_amp_enable; + //assign rd_data = {{DATA_WIDTH-8-CLOCK_DIV_WIDTH{1'b0}}, div_count, {7{1'b0}}, channel_enable}; - assign rd_data = {8'b0, amp_start, {6{1'b0}}, noise_enable, channel_enable}; + assign rd_data = {8'b0, amp_start, + {4{1'b0}}, amp_phase, direct_amp_enable, noise_enable, channel_enable}; assign amp_val = amp_out; assign running = channel_enable; + wire ctl_reg_write = wr_en && (reg_sel == TDRAU_REG_CTL); + /* channel enable flag */ always @(posedge clk) begin if(reset) channel_enable <= 0; - else if (wr_en && (reg_sel == TDRAU_REG_CTL)) + else if (ctl_reg_write) channel_enable <= wr_data[0]; end @@ -97,7 +102,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) ( begin if(reset) noise_enable <= 0; - else if (wr_en && (reg_sel == TDRAU_REG_CTL)) + else if (ctl_reg_write) noise_enable <= wr_data[1]; end @@ -107,7 +112,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) ( if (reset) lfsr <= LFSR_INIT; else - if (wr_en && (reg_sel == TDRAU_REG_CTL) && wr_data[1]) + if (ctl_reg_write && wr_data[1]) lfsr <= LFSR_INIT; else if (channel_enable && noise_enable) @@ -119,6 +124,15 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) ( assign noise_out = lfsr[0] ? amp_start : ~amp_start; + /* direct amplitude enable flag */ + always @(posedge clk) + begin + if(reset) + direct_amp_enable <= 0; + else if (ctl_reg_write) + direct_amp_enable <= wr_data[2]; + end + /* amplitude out */ always @(posedge clk) begin @@ -132,8 +146,9 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) ( begin if (div_count == 0) // invert amplitude on clock tick begin - amp_out <= noise_enable ? noise_out : - amp_phase ? amp_start : ~amp_start; + amp_out <= direct_amp_enable ? amp_start : + noise_enable ? noise_out : + amp_phase ? amp_start : ~amp_start; amp_phase <= ~amp_phase; end end @@ -141,7 +156,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) ( amp_out <= 0; // reset phase bit when enabling the channel - if (wr_en && (reg_sel == TDRAU_REG_CTL) && wr_data[0]) + if (ctl_reg_write && wr_data[0]) // when channel is enabled, phase will be flipped on next tick // because div_count will become zero amp_phase <= 1; diff --git a/tridoracpu/tridoracpu.xpr b/tridoracpu/tridoracpu.xpr index ba7a2ef..4bbcb9d 100644 --- a/tridoracpu/tridoracpu.xpr +++ b/tridoracpu/tridoracpu.xpr @@ -356,12 +356,14 @@ - + - + + Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, applying lower thresholds for use of carry chain in comparators and also area optimized mux optimizations. + - + @@ -381,7 +383,9 @@ - + + Default settings for Implementation. + From 2735b80fecceeff6f0c1201ca5efed9a0bcd9fc1 Mon Sep 17 00:00:00 2001 From: slederer Date: Mon, 29 Sep 2025 20:40:07 +0200 Subject: [PATCH 2/2] tdraudio: remove unneeded status flags, tweak project settings --- tridoracpu/tridoracpu.srcs/tdraudio.v | 4 ++-- tridoracpu/tridoracpu.xpr | 33 +++++++++++++++------------ 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/tridoracpu/tridoracpu.srcs/tdraudio.v b/tridoracpu/tridoracpu.srcs/tdraudio.v index 9cb1d74..9e3721f 100644 --- a/tridoracpu/tridoracpu.srcs/tdraudio.v +++ b/tridoracpu/tridoracpu.srcs/tdraudio.v @@ -46,7 +46,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) ( //assign rd_data = {{DATA_WIDTH-8-CLOCK_DIV_WIDTH{1'b0}}, div_count, {7{1'b0}}, channel_enable}; assign rd_data = {8'b0, amp_start, - {4{1'b0}}, amp_phase, direct_amp_enable, noise_enable, channel_enable}; + {6{1'b0}}, amp_phase, channel_enable}; assign amp_val = amp_out; assign running = channel_enable; @@ -146,7 +146,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) ( begin if (div_count == 0) // invert amplitude on clock tick begin - amp_out <= direct_amp_enable ? amp_start : + amp_out <= direct_amp_enable ? amp_start : noise_enable ? noise_out : amp_phase ? amp_start : ~amp_start; amp_phase <= ~amp_phase; diff --git a/tridoracpu/tridoracpu.xpr b/tridoracpu/tridoracpu.xpr index 4bbcb9d..9541c3d 100644 --- a/tridoracpu/tridoracpu.xpr +++ b/tridoracpu/tridoracpu.xpr @@ -356,15 +356,12 @@ - + - - Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, applying lower thresholds for use of carry chain in comparators and also area optimized mux optimizations. + + Vivado Synthesis Defaults - - - - + @@ -381,18 +378,26 @@ - + - - Default settings for Implementation. + + To compensate for optimistic delay estimation, add extra delay cost to long distance and high fanout connections. low setting, least pessimistic) - + + + - + + + - - + + + + + +