slederer/Tridora-CPU
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base: slederer:2735b80fecceeff6f0c1201ca5efed9a0bcd9fc1
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slederer:main
slederer:tdraudio-pcm
slederer:tdraudio
slederer:dcache
slederer:vga480
slederer:inscache
slederer:sasm-linker
slederer:October-2025-Update
slederer:April-2025-Update
..
compare: slederer:57430a4df69ffb7e519d2ac48915eb6eb84568a8
Branches Tags
slederer:main
slederer:tdraudio-pcm
slederer:tdraudio
slederer:dcache
slederer:vga480
slederer:inscache
slederer:sasm-linker
slederer:October-2025-Update
slederer:April-2025-Update

No commits in common. "2735b80fecceeff6f0c1201ca5efed9a0bcd9fc1" and "57430a4df69ffb7e519d2ac48915eb6eb84568a8" have entirely different histories.
2735b80fec ... 57430a4df6

2 changed files with 19 additions and 43 deletions
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29
tridoracpu/tridoracpu.srcs/tdraudio.v
View file

@ -42,22 +42,17 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
reg [LFSR_WIDTH-1:0] lfsr; reg [LFSR_WIDTH-1:0] lfsr;
wire [AMP_WIDTH-1:0] noise_out; wire [AMP_WIDTH-1:0] noise_out;
reg direct_amp_enable;
//assign rd_data = {{DATA_WIDTH-8-CLOCK_DIV_WIDTH{1'b0}}, div_count, {7{1'b0}}, channel_enable}; //assign rd_data = {{DATA_WIDTH-8-CLOCK_DIV_WIDTH{1'b0}}, div_count, {7{1'b0}}, channel_enable};
assign rd_data = {8'b0, amp_start, assign rd_data = {8'b0, amp_start, {6{1'b0}}, noise_enable, channel_enable};
{6{1'b0}}, amp_phase, channel_enable};
assign amp_val = amp_out; assign amp_val = amp_out;
assign running = channel_enable; assign running = channel_enable;
wire ctl_reg_write = wr_en && (reg_sel == TDRAU_REG_CTL);
/* channel enable flag */ /* channel enable flag */
always @(posedge clk) always @(posedge clk)
begin begin
if(reset) if(reset)
channel_enable <= 0; channel_enable <= 0;
else if (ctl_reg_write) else if (wr_en && (reg_sel == TDRAU_REG_CTL))
channel_enable <= wr_data[0]; channel_enable <= wr_data[0];
end end
@ -102,7 +97,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
begin begin
if(reset) if(reset)
noise_enable <= 0; noise_enable <= 0;
else if (ctl_reg_write) else if (wr_en && (reg_sel == TDRAU_REG_CTL))
noise_enable <= wr_data[1]; noise_enable <= wr_data[1];
end end
@ -112,7 +107,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
if (reset) if (reset)
lfsr <= LFSR_INIT; lfsr <= LFSR_INIT;
else else
if (ctl_reg_write && wr_data[1]) if (wr_en && (reg_sel == TDRAU_REG_CTL) && wr_data[1])
lfsr <= LFSR_INIT; lfsr <= LFSR_INIT;
else else
if (channel_enable && noise_enable) if (channel_enable && noise_enable)
@ -124,15 +119,6 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
assign noise_out = lfsr[0] ? amp_start : ~amp_start; assign noise_out = lfsr[0] ? amp_start : ~amp_start;
/* direct amplitude enable flag */
always @(posedge clk)
begin
if(reset)
direct_amp_enable <= 0;
else if (ctl_reg_write)
direct_amp_enable <= wr_data[2];
end
/* amplitude out */ /* amplitude out */
always @(posedge clk) always @(posedge clk)
begin begin
@ -146,9 +132,8 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
begin begin
if (div_count == 0) // invert amplitude on clock tick if (div_count == 0) // invert amplitude on clock tick
begin begin
amp_out <= direct_amp_enable ? amp_start : amp_out <= noise_enable ? noise_out :
noise_enable ? noise_out : amp_phase ? amp_start : ~amp_start;
amp_phase ? amp_start : ~amp_start;
amp_phase <= ~amp_phase; amp_phase <= ~amp_phase;
end end
end end
@ -156,7 +141,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
amp_out <= 0; amp_out <= 0;
// reset phase bit when enabling the channel // reset phase bit when enabling the channel
if (ctl_reg_write && wr_data[0]) if (wr_en && (reg_sel == TDRAU_REG_CTL) && wr_data[0])
// when channel is enabled, phase will be flipped on next tick // when channel is enabled, phase will be flipped on next tick
// because div_count will become zero // because div_count will become zero
amp_phase <= 1; amp_phase <= 1;

33
tridoracpu/tridoracpu.xpr
View file

@ -356,12 +356,13 @@
</Simulator> </Simulator>
</Simulators> </Simulators>
<Runs Version="1" Minor="22"> <Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, lowering multiplier threshold of inference into DSP blocks, moving shift register into BRAM, applying lower thresholds for use of carry chain in comparators and also area optimized mux optimizations" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"> <StratHandle Name="Flow_AreaOptimized_medium" Flow="Vivado Synthesis 2024"/>
<Desc>Vivado Synthesis Defaults</Desc> <Step Id="synth_design">
</StratHandle> <Option Id="ControlSetOptThreshold">1</Option>
<Step Id="synth_design"/> <Option Id="Directive">2</Option>
</Step>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/> <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
@ -378,26 +379,16 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="To compensate for optimistic delay estimation, add extra delay cost to long distance and high fanout connections. low setting, least pessimistic)" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Performance_NetDelay_low" Flow="Vivado Implementation 2024"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Desc>To compensate for optimistic delay estimation, add extra delay cost to long distance and high fanout connections. low setting, least pessimistic)</Desc>
</StratHandle>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"> <Step Id="opt_design"/>
<Option Id="Directive">0</Option>
</Step>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>
<Step Id="place_design"> <Step Id="place_design"/>
<Option Id="Directive">3</Option>
</Step>
<Step Id="post_place_power_opt_design"/> <Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"> <Step Id="phys_opt_design"/>
<Option Id="Directive">2</Option> <Step Id="route_design"/>
</Step>
<Step Id="route_design">
<Option Id="Directive">1</Option>
</Step>
<Step Id="post_route_phys_opt_design"/> <Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"> <Step Id="write_bitstream">
<Option Id="BinFile">1</Option> <Option Id="BinFile">1</Option>