diff --git a/tridoracpu/tridoracpu.srcs/dram_bridge.v b/tridoracpu/tridoracpu.srcs/dram_bridge.v
index d4f798b..9bd2a92 100644
--- a/tridoracpu/tridoracpu.srcs/dram_bridge.v
+++ b/tridoracpu/tridoracpu.srcs/dram_bridge.v
@@ -165,7 +165,7 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
assign app_wdf_data = { {4{mem_write_data}} };
assign mem_wait = (dram_read_enable & ~read_inprogress) |
- (mem_write_enable & ~dcache_hit & (~app_wdf_rdy | ~app_rdy)) |
+ (mem_write_enable & (~app_wdf_rdy | ~app_rdy)) |
(read_inprogress & ~app_rd_data_valid);
assign app_en = (dram_read_enable & ~read_inprogress) |
diff --git a/tridoracpu/tridoracpu.srcs/tdraudio.v b/tridoracpu/tridoracpu.srcs/tdraudio.v
index 9e3721f..cef16da 100644
--- a/tridoracpu/tridoracpu.srcs/tdraudio.v
+++ b/tridoracpu/tridoracpu.srcs/tdraudio.v
@@ -1,7 +1,8 @@
`timescale 1ns / 1ps
-// waveform generator module (only pulse wave for now)
-module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
+// waveform generator module (pulse wave or noise)
+module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22,
+ AMP_WIDTH=16, AMP_BIAS=32768) (
input wire clk,
input wire reset,
input wire [1:0] reg_sel,
@@ -18,11 +19,6 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
localparam TDRAU_REG_CLK = 1; /* clock divider register */
localparam TDRAU_REG_AMP = 2; /* amplitude (volume) register */
-// localparam LFSR_WIDTH = 15;
-// localparam LFSR_TAP_IDX_1 = 3;
-// localparam LFSR_TAP_IDX_2 = 0;
-// localparam LFSR_INIT = 'h7672;
-
// localparam LFSR_WIDTH = 18;
// localparam LFSR_TAP_IDX_1 = 17;
// localparam LFSR_TAP_IDX_2 = 10;
@@ -138,7 +134,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
begin
if (reset)
begin
- amp_out <= 0;
+ amp_out <= AMP_BIAS;
amp_phase <= 1;
end
else
@@ -153,7 +149,7 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) (
end
end
else
- amp_out <= 0;
+ amp_out <= AMP_BIAS;
// reset phase bit when enabling the channel
if (ctl_reg_write && wr_data[0])
@@ -214,6 +210,8 @@ module tdraudio #(DATA_WIDTH=32) (
wire running = chan0_running || chan1_running || chan2_running || chan3_running;
+ reg was_running;
+
assign rd_data = chan0_sel ? chan0_rd_data :
chan1_sel ? chan1_rd_data :
chan2_sel ? chan2_rd_data :
@@ -247,6 +245,15 @@ module tdraudio #(DATA_WIDTH=32) (
assign shutdown_n = running;
+ /* detect shutdown */
+ always @(posedge clk)
+ begin
+ if (reset)
+ was_running <= 0;
+ else
+ was_running <= running;
+ end
+
/* delta-sigma DAC */
always @(posedge clk)
begin
@@ -255,6 +262,9 @@ module tdraudio #(DATA_WIDTH=32) (
else
if (running)
deltasigma_acc <= deltasigma_acc[DAC_WIDTH-1:0] + amp_sum;
+ else
+ if (!running && was_running) // clear accumulator on shutdown
+ deltasigma_acc <= 0;
end
/* 1-bit audio output */
diff --git a/tridoracpu/tridoracpu.xpr b/tridoracpu/tridoracpu.xpr
index 9541c3d..15b43f2 100644
--- a/tridoracpu/tridoracpu.xpr
+++ b/tridoracpu/tridoracpu.xpr
@@ -378,10 +378,10 @@
-
+
-
- To compensate for optimistic delay estimation, add extra delay cost to long distance and high fanout connections. low setting, least pessimistic)
+
+ Uses multiple algorithms for optimization, placement, and routing to get potentially better results.
@@ -389,14 +389,14 @@
-
+
-
+
-
+