Commit graph

2 commits

Author SHA1 Message Date
slederer
91b693979d Makefile and constraints for GateMateA1-EVB board 2025-02-23 00:47:26 +01:00
slederer
a441e7e042 import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00