Commit graph

108 commits

Author SHA1 Message Date
slederer
833861e377 doc/tridoracpu: fix INC example 2024-10-04 11:51:35 +02:00
slederer
4af05753e5 docs: add UART documentation 2024-10-04 00:37:57 +02:00
slederer
9f40caa45e README: add video and doc links 2024-10-04 00:07:34 +02:00
slederer
9fd9fd1fb9 README.md: add images 2024-09-29 03:32:01 +02:00
slederer
bf0f5c8c79 README.md: small correction 2024-09-27 22:38:37 +02:00
slederer
a441e7e042 import Vivado project, rearrange Verilog sources 2024-09-27 22:14:57 +02:00
slederer
18b95b6bb6 editor: handle DEL at prompt()
README: small corrections
2024-09-27 02:18:14 +02:00
slederer
60db522e87 initial commit 2024-09-19 14:12:22 +02:00