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vgafb: simplify maskgen a bit to avoid timing problems

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slederer 2026-02-01 22:08:06 +01:00
parent bf813fac1d
commit f90d52926f
4 changed files with 33 additions and 37 deletions
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3
examples/sprites.s
View file

@ -97,6 +97,7 @@ PS_LOOP1:
STORE.B FB_SHIFTCOUNT STORE.B FB_SHIFTCOUNT
LOAD.B FB_SHIFTERM ; get shifted mask LOAD.B FB_SHIFTERM ; get shifted mask
NOT
LOAD.B FB_IO ; and background pixel data LOAD.B FB_IO ; and background pixel data
AND ; remove foreground pixels AND ; remove foreground pixels
@ -130,6 +131,7 @@ PS_NEXT_STRIPE:
STORE.B FB_MASKGEN ; store to mask reg to get new mask STORE.B FB_MASKGEN ; store to mask reg to get new mask
LOAD.B FB_MASKGEN ; get mask for spill bits + shifted pixels LOAD.B FB_MASKGEN ; get mask for spill bits + shifted pixels
NOT
LOAD.B FB_IO ; get vmem data LOAD.B FB_IO ; get vmem data
AND ; remove foreground pixels from bg AND ; remove foreground pixels from bg
@ -147,6 +149,7 @@ PS_NEXT_STRIPE:
DUP DUP
STORE.B FB_MASKGEN STORE.B FB_MASKGEN
LOAD.B FB_MASKGEN ; get sprite mask for spill bits LOAD.B FB_MASKGEN ; get sprite mask for spill bits
NOT
LOAD.B FB_IO ; load next vmem word LOAD.B FB_IO ; load next vmem word
AND ; apply sprite mask AND ; apply sprite mask

32
tridoracpu/tridoracpu.srcs/vgafb.v
View file

@ -341,28 +341,28 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
always @(posedge cpu_clk) always @(posedge cpu_clk)
begin begin
acc_mask_buf <= { acc_mask_buf <= {
{4{~|{acc_mask_in[31:28]}}}, {4{|{acc_mask_in[31:28]}}},
{4{~|{acc_mask_in[27:24]}}}, {4{|{acc_mask_in[27:24]}}},
{4{~|{acc_mask_in[23:20]}}}, {4{|{acc_mask_in[23:20]}}},
{4{~|{acc_mask_in[19:16]}}}, {4{|{acc_mask_in[19:16]}}},
{4{~|{acc_mask_in[15:12]}}}, {4{|{acc_mask_in[15:12]}}},
{4{~|{acc_mask_in[11:8]}}}, {4{|{acc_mask_in[11:8]}}},
{4{~|{acc_mask_in[7:4]}}}, {4{|{acc_mask_in[7:4]}}},
{4{~|{acc_mask_in[3:0]}}} {4{|{acc_mask_in[3:0]}}}
}; };
end end
always @(posedge cpu_clk) always @(posedge cpu_clk)
begin begin
acc_shiftmask_buf = { acc_shiftmask_buf = {
{4{~|{acc_shifter_out_h[31:28]}}}, {4{|{acc_shifter_out_h[31:28]}}},
{4{~|{acc_shifter_out_h[27:24]}}}, {4{|{acc_shifter_out_h[27:24]}}},
{4{~|{acc_shifter_out_h[23:20]}}}, {4{|{acc_shifter_out_h[23:20]}}},
{4{~|{acc_shifter_out_h[19:16]}}}, {4{|{acc_shifter_out_h[19:16]}}},
{4{~|{acc_shifter_out_h[15:12]}}}, {4{|{acc_shifter_out_h[15:12]}}},
{4{~|{acc_shifter_out_h[11:8]}}}, {4{|{acc_shifter_out_h[11:8]}}},
{4{~|{acc_shifter_out_h[7:4]}}}, {4{|{acc_shifter_out_h[7:4]}}},
{4{~|{acc_shifter_out_h[3:0]}}} {4{|{acc_shifter_out_h[3:0]}}}
}; };
end end
`endif `endif

34
tridoracpu/tridoracpu.xpr
View file

@ -356,14 +356,12 @@
</Simulator> </Simulator>
</Simulators> </Simulators>
<Runs Version="1" Minor="22"> <Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Performs optimizations which creates alternative logic technology mapping, including disabling LUT combining, forcing F7/F8/F9 to logic, increasing the threshold of shift register inference." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Flow_AlternateRoutability" Flow="Vivado Synthesis 2024"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Step Id="synth_design"> <Desc>Vivado Synthesis Defaults</Desc>
<Option Id="Directive">3</Option> </StratHandle>
<Option Id="NoCombineLuts">1</Option> <Step Id="synth_design"/>
<Option Id="ShregMinSize">10</Option>
</Step>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/> <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
@ -380,24 +378,18 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Best predicted directive for place_design." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Performance_Auto_1" Flow="Vivado Implementation 2024"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"> <Step Id="opt_design"/>
<Option Id="Directive">0</Option>
</Step>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>
<Step Id="place_design"> <Step Id="place_design"/>
<Option Id="Directive">20</Option>
</Step>
<Step Id="post_place_power_opt_design"/> <Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"> <Step Id="phys_opt_design"/>
<Option Id="Directive">2</Option> <Step Id="route_design"/>
</Step>
<Step Id="route_design">
<Option Id="Directive">1</Option>
</Step>
<Step Id="post_route_phys_opt_design"/> <Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/> <Step Id="write_bitstream"/>
</Strategy> </Strategy>

1
utils/tdrimg.py
View file

@ -614,6 +614,7 @@ def create_image_with_stuff(imgfile):
slotnr = putfile("../examples/benchmarks.pas", None , f, part, partstart, slotnr) slotnr = putfile("../examples/benchmarks.pas", None , f, part, partstart, slotnr)
slotnr = putfile("../examples/animate.pas", None , f, part, partstart, slotnr) slotnr = putfile("../examples/animate.pas", None , f, part, partstart, slotnr)
slotnr = putfile("../examples/graphbench.pas", None , f, part, partstart, slotnr)
slotnr = putfile("../examples/sprites.inc", None , f, part, partstart, slotnr) slotnr = putfile("../examples/sprites.inc", None , f, part, partstart, slotnr)
slotnr = putfile("../examples/sprites.s", None , f, part, partstart, slotnr) slotnr = putfile("../examples/sprites.s", None , f, part, partstart, slotnr)
slotnr = putfile("../examples/background.pict", None , f, part, partstart, slotnr) slotnr = putfile("../examples/background.pict", None , f, part, partstart, slotnr)