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README: add video and doc links

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slederer 2024-10-03 23:00:19 +02:00
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README.md
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@ -6,8 +6,7 @@ Everything is as simple as possible while still being reasonably useful.
Everything is open source, so you can read, understand and modify the whole system, hardware and software. Everything is open source, so you can read, understand and modify the whole system, hardware and software.
## Overview ## Overview
- homebrew CPU - homebrew CPU written in Verilog implemented on an FPGA
- Verilog FPGA SoC
- 32-bit word-oriented stack machine architecture - 32-bit word-oriented stack machine architecture
- running at 83 MHz on an Arty-A7 board with four clocks per instruction - running at 83 MHz on an Arty-A7 board with four clocks per instruction
- has its own instruction set architecture, compatible with nothing - has its own instruction set architecture, compatible with nothing
@ -25,10 +24,13 @@ Everything is open source, so you can read, understand and modify the whole syst
## Demos ## Demos
### Videos ### Videos
- (Video hello world)
- (Video lines)
### Still Pictures |Compiling and Running Hello-World|Moving Lines Demo|
|---|---|
|<video src="https://insignificance.de/tridora/tdr-hello.mp4" controls></video>|<video src="https://insignificance.de/tridora/tdr-lines.mp4" controls></video>|
### Pictures
|Mandelbrot|Image Viewer|Game of Life| |Mandelbrot|Image Viewer|Game of Life|
|---|---|---| |---|---|---|
@ -71,3 +73,11 @@ Everything is open source, so you can read, understand and modify the whole syst
- run synthesis, implementation and bitstream generation (Flow -> Generate Bitstream) - run synthesis, implementation and bitstream generation (Flow -> Generate Bitstream)
- program your device (Flow -> Open Hardware Manager), the bitstream file should be in **tridoracpu/tridoracpu.runs/impl_1** - program your device (Flow -> Open Hardware Manager), the bitstream file should be in **tridoracpu/tridoracpu.runs/impl_1**
- the bitstream file for (temporarily) programming your device is named **top.bit**, the file for flashing your device is named **top.bin** - the bitstream file for (temporarily) programming your device is named **top.bit**, the file for flashing your device is named **top.bin**
## Documentation
- Instruction Reference (doc/tridoracpu.md)
- Memory Layout (doc/mem.md)
- SD-Card controller (doc/spisd.md)
- VGA controller (doc/vga.md)
More documentation is coming as time permits.

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doc/mem.md
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@ -19,8 +19,7 @@ The lower two bits of the address can be viewed as a byte address (0-3) within t
The _BSEL_ and _BPLC_ instructions are designed to assist with accessing bytes within a word. The _BSEL_ and _BPLC_ instructions are designed to assist with accessing bytes within a word.
Because memory is always accessed in words, the CPU is neither big-endian nor little-endian. However, the _BSEL_ and _BPLC_ The byte ordering is big-endian.
instructions are big-endian when accessing bytes within a word, so the system can be considered big-endian.
## Accessing the I/O Area ## Accessing the I/O Area
The I/O area organizes memory slightly different. Here, pointing out individual bytes is not very useful, so the I/O controllers use register addresses with increments of one. In practice, there is only the VGA framebuffer controller which uses multiple registers. The I/O area organizes memory slightly different. Here, pointing out individual bytes is not very useful, so the I/O controllers use register addresses with increments of one. In practice, there is only the VGA framebuffer controller which uses multiple registers.