vga framebuffer: use 640x480@60Hz video timings
- we still can only display 400 lines, so 80 blank lines are added at the bottom - we get square pixels this way and are hopefully more compatible with monitors and other devices like scan converters and capture cards
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slederer
parent
e08d610aef
commit
ecff04a7a0
2 changed files with 39 additions and 18 deletions
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@ -6,8 +6,11 @@
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// Learn more at https://projectf.io
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//128K video memory is not enough for 640x480x4
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`define RES_640_400
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//`define RES_640_400
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//`define RES_1024_768
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// RES_640_480 mode displays 400 lines with 640x480/60 video timings,
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// adding blank lines at the bottom
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`define RES_640_480
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module display_timings #(
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H_RES=640, // horizontal resolution (pixels)
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@ -126,6 +129,8 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
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localparam COLOR_WIDTH = 12;
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localparam PALETTE_WIDTH = 4;
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localparam signed PIC_LINES = 400; // visible picture lines
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// Display Clocks
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wire pix_clk = CLK; // pixel clock
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wire clk_lock = 1; // clock locked?
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@ -202,6 +207,18 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
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.V_BP(35),
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.H_POL(0),
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.V_POL(1)
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`endif
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`ifdef RES_640_480
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.H_RES(640), // 640 800 1280 1920
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.V_RES(480), // 480 600 720 1080
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.H_FP(16), // 16 40 110 88
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.H_SYNC(96), // 96 128 40 44
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.H_BP(48), // 48 88 220 148
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.V_FP(10), // 10 1 5 4
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.V_SYNC(2), // 2 4 5 5
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.V_BP(33), // 33 23 20 36
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.H_POL(0), // 0 1 1 1
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.V_POL(0) // 0 1 1 1
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`endif
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)
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display_timings_inst (
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@ -217,6 +234,8 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
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.o_sy(sy)
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);
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wire pic_enable = (sy >= 0) && (sy < PIC_LINES); // when to display pixels from VRAM
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wire [7:0] red;
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wire [7:0] green;
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wire [7:0] blue;
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@ -288,7 +307,7 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
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// 12 bit RGB palette
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assign VGA_HS = h_sync;
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assign VGA_VS = v_sync;
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assign VGA_R = de ? color_data[11:8] : 4'b0;
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assign VGA_G = de ? color_data[7:4] : 4'b0;
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assign VGA_B = de ? color_data[3:0] : 4'b0;
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assign VGA_R = (pic_enable && de) ? color_data[11:8] : 4'b0;
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assign VGA_G = (pic_enable && de) ? color_data[7:4] : 4'b0;
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assign VGA_B = (pic_enable && de) ? color_data[3:0] : 4'b0;
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endmodule
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@ -351,7 +351,9 @@
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<Runs Version="1" Minor="22">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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@ -361,9 +363,7 @@
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</Run>
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<Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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@ -371,21 +371,25 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Increase placer effort in the post-placement optimization phase, and disable timing relaxation in the router." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Best predicted directive for place_design." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Performance_RefinePlacement" Flow="Vivado Implementation 2020"/>
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<StratHandle Name="Performance_Auto_1" Flow="Vivado Implementation 2024">
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<Desc>Best predicted directive for place_design.</Desc>
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</StratHandle>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="opt_design">
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<Option Id="Directive">0</Option>
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</Step>
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<Step Id="power_opt_design"/>
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<Step Id="place_design">
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<Option Id="Directive">7</Option>
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<Option Id="Directive">20</Option>
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</Step>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design">
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<Option Id="Directive">0</Option>
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<Option Id="Directive">2</Option>
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</Step>
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<Step Id="route_design">
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<Option Id="Directive">0</Option>
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<Option Id="Directive">1</Option>
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</Step>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream">
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@ -393,15 +397,13 @@
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</Step>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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